74ACTQ533PC ,Quiet Series Octal Transparent Latch with 3-STATE OutputsFunctional DescriptionThe ACTQ533 contains eight D-type latches with 3-STATE transition of LE. The ..
74ACTQ541 ,Quiet Series Octal Buffer/Line Driver with TRI-STATE OutputsFeaturesYI and I reduced by 50%The ’ACTQ541 is an octal buffer/line driver designed to beCC OZYempl ..
74ACTQ541MTC ,Quiet Series Octal Buffer/Line Driver with 3-STATE Outputs74ACTQ541 Quiet Series Octal Buffer/Line Driver with 3-STATE OutputsMarch 1993Revised March 200574A ..
74ACTQ541SCX ,Quiet Series Octal Buffer/Line Driver with 3-STATE Outputs74ACTQ541 Quiet Series Octal Buffer/Line Driver with 3-STATE OutputsMarch 1993Revised March 200574A ..
74ACTQ541SCX ,Quiet Series Octal Buffer/Line Driver with 3-STATE OutputsFeaturesThe 74ACTQ541 is an octal buffer/line driver designed to
74ACTQ533PC
Quiet Series Octal Transparent Latch with 3-STATE Outputs
74ACTQ533 Quiet Series Octal Transparent Latch with 3-STATE Outputs January 1990 Revised November 1999 74ACTQ533 Quiet Series Octal Transparent Latch with 3-STATE Outputs General Description Features The ACTQ533 consists of eight latches with 3-STATE out-I and I reduced by 50% CC OZ puts for bus organized system applications. The flip-flops Guaranteed simultaneous switching noise level and appear transparent to the data when Latch Enable (LE) is dynamic threshold performance HIGH. When LE is LOW, the data satisfying the input tim- Guaranteed pin-to-pin skew AC performance ing requirements is latched. Data appears on the bus when Improved latch up immunity the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.Eight latches in a single package The ACTQ533 utilizes Fairchild Quiet Series technology3-STATE outputs drive bus lines or buffer memory to guarantee quiet output switching and improve dynamic address registers threshold performance. FACT Quiet Series features GTO Outputs source/sink 24 mA output control and undershoot corrector in addition to a Inverted version of the ACTQ373 split ground bus for superior performance. 4 kV minimum ESD immunity Ordering Code: Order Number Package Number Package Description 74ACTQ533SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 74ACTQ533MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACTQ533PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description D –D Data Inputs 0 7 LE Latch Enable Input OE Output Enable Input O –O 3-STATE Latch Outputs 0 7 FACT, FACT Quiet Series, and GTO are trademarks of . © 1999 DS010630
