74ACTQ32SCX ,Quiet Series Quad 2-Input OR Gate74ACTQ32 Quiet Series Quad 2-Input OR GateMarch 1993Revised July 200374ACTQ32Quiet Series Quad 2-In ..
74ACTQ32SJ ,Quiet Series Quad 2-Input OR GateElectrical CharacteristicsV T = +25°CT = −55°C to +125°CT = −40°C to +85°CCC A A ASymbol Parameter ..
74ACTQ32SJX ,Quiet Series Quad 2-Input OR GateFeaturesThe ACTQ320 contains four, 2-input OR gates and utilizes
74ACTQ32PC-74ACTQ32SCX-74ACTQ32SJ-74ACTQ32SJX
Quiet Series Quad 2-Input OR Gate
74ACTQ32 Quiet Series Quad 2-Input OR Gate March 1993 Revised July 2003 74ACTQ32 Quiet Series Quad 2-Input OR Gate General Description Features The ACTQ320 contains four, 2-input OR gates and utilizesI reduced by 50% CC Fairchild Quiet Series technology to guarantee quiet output Guaranteed simultaneous switching noise level and switching and improved dynamic threshold performance. dynamic threshold performance FACT Quiet Series features GTO output control and Improved latch-up immunity undershoot corrector in addition to a split ground bus for superior ACMOS performance.Minimum 4 kV ESD protection TTL-compatible inputs Outputs source/sink 24 mA Ordering Code: Order Number Package Number Package Description 74ACTQ32SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74ACTQ32SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACTQ32PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Pin Names Descriptions A , B Inputs n n O Outputs n FACT, FACT Quiet Series, and GTO are trademarks of . © 2003 DS010893
