74ACT280 ,9 BIT PARITY GENERATOR/CHECKER74ACT2809 BIT PARITY GENERATOR/CHECKER ■ HIGH SPEED: t = 7ns (TYP.) at V = 5VPD CC■ LOW POWER DISS ..
74ACT280M ,9 BIT PARITY GENERATOR/CHECKER74ACT2809 BIT PARITY GENERATOR/CHECKER ■ HIGH SPEED: t = 7ns (TYP.) at V = 5VPD CC■ LOW POWER DISS ..
74ACT299 ,8-Input Universal Shift/Storage Register with Common I/O Pins74ACT2998 BIT PIPO SHIFT REGISTERWITH ASYNCHRONOUS CLEAR ■ HIGH SPEED: f = 240MHz (TYP.) at V = 5V ..
74ACT299 ,8-Input Universal Shift/Storage Register with Common I/O Pins
74ACT299SCX ,8-Input Universal Shift/Storage Register with Common I/O PinsFeaturesThe AC/ACT299 is an 8-bit universal shift/storage register
74ACT280
9 BIT PARITY GENERATOR/CHECKER
1/9April 2001 HIGH SPEED: tPD = 7ns (TYP .) at VCC = 5V LOW POWER DISSIPATION:CC = 4μA(MAX.) at TA =25°C COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.), VIL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:OH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:CC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 280 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74ACT280 is an advanced high-speed CMOS
9 BIT PARITY GENERATOR CHECKER
fabricated with sub-micron silicon gate and
double-layer metal wiring C2 MOS tecnology.
It is composed of nine data inputs (A to I) and odd/
even parity outputs (ΣODD and ΣEVEN). The nine
data inputs control the output conditions. When
the number of high level input is odd, ΣODD
output is kept high and ΣEVEN output low.
Conservely, when the output is even, ΣEVEN
output is kept high and ΣODD low.
The IC generates either odd or even parity making
it flexible application. The word-length capability is
easly expanded by cascading.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74ACT2809 BIT PARITY GENERATOR/CHECKER
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74ACT2802/9
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE
LOGIC DIAGRAM
74ACT2803/9
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS 1) VIN from 0.8V to 2.0V
74ACT2804/9
DC SPECIFICATIONS 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) (*) Voltage range is 5.0V ± 0.5V
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
74ACT2805/9
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
