IC Phoenix
 
Home ›  776 > 74ACT240,Octal Buffer/Line Driver with 3-STATE Outputs
74ACT240 Fast Delivery,Good Price
Part Number:
If you need More Quantity or Better Price,Welcom Any inquiry.
We available via phone +865332716050 Email
Partno Mfg Dc Qty AvailableDescript
74ACT240FSCN/a30avaiOctal Buffer/Line Driver with 3-STATE Outputs


74ACT240 ,Octal Buffer/Line Driver with 3-STATE OutputsFeaturesThe AC/ACT240 is an octal buffer and line driver designed

74ACT240
Octal Buffer/Line Driver with 3-STATE Outputs
74AC240 • 74ACT240 Octal Buffer/Line Driver with 3-STATE Outputs November 1988 Revised November 1999 74AC240  74ACT240 Octal Buffer/Line Driver with 3-STATE Outputs General Description Features The AC/ACT240 is an octal buffer and line driver designedI and I reduced by 50% CC OZ to be employed as a memory address driver, clock driver Inverting 3-STATE outputs drive bus lines or buffer and bus oriented transmitter or receiver which provides memory address registers improved PC board density. Outputs source/sink 24 mA ACT240 has TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74AC240SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 74AC240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC240MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,4.4mm Wide 74AC240PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACT240SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 74ACT240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT240MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,4.4mm Wide 74ACT240PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions IEEE/IEC Pin Names Description OE , OE 3-STATE Output Enable Inputs 1 2 I –I Inputs 0 7 O –O Outputs 0 7 Truth Tables Inputs Outputs OE I (Pins 12, 14, 16, 18) 1 n LL H LH L HX Z Connection Diagram Inputs Outputs OE I (Pins 3, 5, 7, 9) 2 n LL H LH L HX Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance FACT is a trademark of . © 1999 DS009941
ic,good price


TEL:86-533-2716050      FAX:86-533-2716790
   

©2020 IC PHOENIX CO.,LIMITED