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74ACT18823FAIRCHILDN/a100avai18-Bit D-Type Flip-Flop with 3-STATE Outputs


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74ACT18823
18-Bit D-Type Flip-Flop with 3-STATE Outputs
74ACT18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs August 1999 Revised October 1999 74ACT18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs General Description Features The ACT18823 contains eighteen non-inverting D-type flip- � Broadside pinout allows for easy board layout flops with 3-STATE outputs and is intended for bus oriented � Separate control logic for each byte applications. The device is byte controlled. A buffered clock � Extra data width for wider address/data paths or buses (CP), Clear (CLR), Clock Enable (EN) and Output Enable carrying parity (OE) are common to each byte and can be shorted � Outputs source/sink 24 mA together for full 18-bit operation. � TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74ACT18823SSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 74ACT18823MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW) n CLR Clear (Active LOW) n EN Clock Enable (Active LOW) n CP Clock Pulse Input n I –I Inputs 0 17 O –O Outputs 0 17 FACT is a trademark of . © 1999 DS500294
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