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Home ›  774 > 74AC377MTCX-74AC377PC-74AC377SC-74AC377SCX-74AC377SJX-74ACT377PC-74ACT377SCX-74ACT377SJ-74ACT377SJX,Octal D-Type Flip-Flop with Clock Enable
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74AC377MTCXFAIRCHILDN/a2500avaiOctal D-Type Flip-Flop with Clock Enable
74AC377MTCXFSCN/a13368avaiOctal D-Type Flip-Flop with Clock Enable
74AC377PCFAIN/a243avaiOctal D-Type Flip-Flop with Clock Enable
74AC377SCFAIRCN/a112avaiOctal D-Type Flip-Flop with Clock Enable
74AC377SCFAIRCHILN/a712avaiOctal D-Type Flip-Flop with Clock Enable
74AC377SCNSN/a70avaiOctal D-Type Flip-Flop with Clock Enable
74AC377SCXFAIRCHILDN/a145avaiOctal D-Type Flip-Flop with Clock Enable
74AC377SJXFAIN/a2000avaiOctal D-Type Flip-Flop with Clock Enable
74ACT377SJXFAIRCN/a2000avaiOctal D-Type Flip-Flop with Clock Enable
74ACT377PCFAIN/a20avaiOctal D-Type Flip-Flop with Clock Enable
74ACT377SCXFAIN/a228avaiOctal D-Type Flip-Flop with Clock Enable
74ACT377SJFSCN/a124avaiOctal D-Type Flip-Flop with Clock Enable
74ACT377SJNSN/a57avaiOctal D-Type Flip-Flop with Clock Enable


74AC377MTCX ,Octal D-Type Flip-Flop with Clock EnableFeaturesThe AC/ACT377 has eight edge-triggered, D-type flip-flops

74AC377MTCX-74AC377PC-74AC377SC-74AC377SCX-74AC377SJX-74ACT377PC-74ACT377SCX-74ACT377SJ-74ACT377SJX
Octal D-Type Flip-Flop with Clock Enable
74AC377 • 74ACT377 Octal D-Type Flip-Flop with Clock Enable November 1988 Revised March 2005 74AC377  74ACT377 Octal D-Type Flip-Flop with Clock Enable General Description Features The AC/ACT377 has eight edge-triggered, D-type flip-flopsI reduced by 50% CC with individual D inputs and Q outputs. The common buff- Ideal for addressable register applications ered Clock (CP) input loads all flip-flops simultaneously, Clock enable for address and data synchronization when the Clock Enable (CE) is LOW. applications The register is fully edge-triggered. The state of each D Eight edge-triggered D-type flip-flops input, one setup time before the LOW-to-HIGH clock transi- Buffered common clock tion, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior toOutputs source/sink 24 mA the LOW-to-HIGH clock transition for predictable operation. See 273 for master reset version See 373 for transparent latch version See 374 for 3-STATE version ACT377 has TTL-compatible inputs Ordering Code: Package Order Number Package Description Number 74AC377SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74AC377SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC377MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC377MTCX_NL MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm (Note 1) Wide 74AC377PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74ACT377SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74ACT377SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT377MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT377PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Connection Diagram Pin Descriptions Pin Names Description D –D Data Inputs 0 7 CE Clock Enable (Active LOW) Q –Q Data Outputs 0 7 CP Clock Pulse Input FACT¥ is a trademark of . © 2005 DS009961
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