IC Phoenix
 
Home ›  773 > 74AC161M,SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
74AC161M Fast Delivery,Good Price
Part Number:
If you need More Quantity or Better Price,Welcom Any inquiry.
We available via phone +865332716050 Email
Partno Mfg Dc Qty AvailableDescript
74AC161MSTN/a182avaiSYNCHRONOUS PRESETTABLE 4-BIT COUNTER


74AC161M ,SYNCHRONOUS PRESETTABLE 4-BIT COUNTER74AC161SYNCHRONOUS PRESETTABLE 4-BIT COUNTER ■ HIGH SPEED: f = 125MHz (TYP.) at V = 5VMAX CC■ LOW ..
74AC161MTCX ,Synchronous Presettable Binary CounterFeaturesThe AC/ACT161 are high-speed synchronous modulo-16

74AC161M
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
1/13July 2001 HIGH SPEED:
fMAX = 125MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION:CC = 8μA(MAX.) at TA =25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28 % VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS:PLH ≅ tPHL OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 161 IMPROVED LATCH-UP IMMUNITY
DESCRIPTION

The 74AC161 is an advanced high-speed CMOS
SYNCRONOUS PRESETTABLE COUNTER
fabricated with sub-micron silicon gate and
double-layer metal wiring C2 MOS tecnology. It is a
4 bit binary counter with Asynchronous Clear.
The circuit have four fundamental modes of
operation, in order of preference: synchronous
reset, parallel load, count-up and hold. Four
control inputs, (CLEAR), (LOAD), (PE) and (TE),
determine the mode of operation as shown in the
Truth Table. A LOW signal on CLEAR overrides
counting and parallel loading and sets all outputs
on LOW state. A LOW signal on LOAD overrides
counting and allows information on Parallel Data
inputs to be loaded into the flip-flop on the next
rising edge of CLOCK. With LOAD and CLEAR
HIGH, PE and TE permit counting when both are
HIGH. Conversely, a LOW signal on either PE and
TE inhibits counting.
The CARRY OUTPUT is HIGH when TE is HIGH
and counter is in state 15.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74AC161

SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74AC161
2/13
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE

X : Don’t Care; A, B, C, D; Logic level of data input; CARRY OUT : TE x QA x QB x QC x QD
LOGIC DIAGRAM
74AC161
3/13
TIMING CHART
74AC161
4/13
ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS

1) VIN from 30% to 70% of VCC
74AC161
5/13
DC SPECIFICATIONS

1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
74AC161
6/13
AC ELECTRICAL CHARACTERISTICS (C
L = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
74AC161
7/13
CAPACITIVE CHARACTERISTICS

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
TEST CIRCUIT

CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: PROPAGATION DELAYS, COUNT MODE (f=1MHz; 50% duty cycle)
ic,good price


TEL:86-533-2716050      FAX:86-533-2716790
   

©2020 IC PHOENIX CO.,LIMITED