74ABT377CMSAX ,Octal D-Type Flip-Flop with Clock Enableapplicationsered Clock (CP) input loads all flip-flops simultaneously
74ABT377CMSAX
Octal D-Type Flip-Flop with Clock Enable
74ABT377 Octal D-Type Flip-Flop with Clock Enable January 1993 Revised November 1999 74ABT377 Octal D-Type Flip-Flop with Clock Enable General Description Features The ABT377 has eight edge-triggered, D-type flip-flopsClock enable for address and data synchronization with individual D inputs and Q outputs. The common buff- applications ered Clock (CP) input loads all flip-flops simultaneouslyEight edge-triggered D-type flip-flops when the Clock Enable (CE) is LOW. Buffered common clock The register is fully edge-triggered. The state of each D See ABT273 for master reset version input, one setup time before the LOW-to-HIGH clock transi- See ABT373 for transparent latch version tion, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior toSee ABT374 for 3-STATE version the LOW-to-HIGH clock transition for predictable operation.Output sink capability of 64 mA, source capability of 32 mA Guaranteed latchup protection High impedance glitch free bus loading during entire power up and power down cycle Non-destructive hot insertion capability Disable time less than enable time to avoid bus contention Ordering Code: Order Number Package Number Package Description 74ABT377CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 74ABT377CSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ABT377CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74ABT377CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Descriptions D –D Data Inputs 0 7 Clock Enable (Active LOW) CE CP Clock Pulse Input Q –Q Data Outputs 0 7 Truth Table Operating Mode Inputs Output Q CP CE D n n Load “1”Ih H Load “0”II L Holdh X No Change (Do Nothing) X H X No Change H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition I = LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition © 1999 DS011550
