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7445N/a50avaiBCD to Decimal Decoders/Drivers


7445 ,BCD to Decimal Decoders/DriversFeaturesThese BCD-to-decimal decoders/drivers consist of eight Full decoding of input logicinverte ..
74454115 , POWER-CHOKE WE-PD 3
74456033 , POWER-CHOKE WE-PD 4
74456033 , POWER-CHOKE WE-PD 4
74456115 , POWER-CHOKE WE-PD 4
74456147 , POWER-CHOKE WE-PD 4
74F574 ,Octal D Flip-Flop with TRI-STATE OutputsFeaturesYInputs and outputs on opposite sides of packageThe ’F574 is a high-speed, low power octal ..
74F574PC ,Octal D-Type Flip-Flop with TRI-STATE OutputsFunctional Description Function TableThe 74F574 consists of eight edge-triggered flip-flops withInp ..
74F574SCX ,Octal D-Type Flip-Flop with 3-STATE OutputsapplicationsThis device is functionally identical to the 74F374 exceptfor the pinouts. Ordering Cod ..
74F574SCX ,Octal D-Type Flip-Flop with 3-STATE Outputs74F574 Octal D-Type Flip-Flop with 3-STATE OutputsApril 1988Revised October 200074F574Octal D-Type ..
74F574SCX ,Octal D-Type Flip-Flop with 3-STATE OutputsFeaturesThe 74F574 is a high-speed, low power octal flip-flop with a

7445
BCD to Decimal Decoders/Drivers
DM7445 BCD to Decimal Decoders/Drivers September 1986 Revised February 2000 DM7445 BCD to Decimal Decoders/Drivers General Description Features These BCD-to-decimal decoders/drivers consist of eight � Full decoding of input logic inverters and ten, four-input NAND gates. The inverters are � 80 mA sink-current capability connected in pairs to make BCD input data available for � All outputs are off for invalid BCD input conditions decoding by the NAND gates. Full decoding of BCD input logic ensures that all outputs remain OFF for all invalid (10–15) binary input conditions. These decoders feature high-performance, NPN output transistors designed for use as indicator/relay drivers, or as open-collector logic-circuit drivers. The high-breakdown output transistors are com- patible for interfacing with most MOS integrated circuits. Ordering Code: Order Number Package Number Package Description DM7445 N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram © 2000 DS006517
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