5962-9091001MRA ,Octal D Flip-Flop with Clock EnableapplicationsThe ’F377 has eight edge-triggered, D-type flip-flops withYindividual D inputs and Q ou ..
5962-9151901MPA ,Dual, Precision JFET High Speed Operational AmplifierCHARACTERISTICSS AOP249A OP249FParameter Symbol Conditions Min Typ Max Min Typ Max UnitOffset Volta ..
5962-9152101MXA ,4-channel Simultaneous Sampling, 12-Bit Data Acquisition SystemSPECIFICATIONSMIN MAXParameter A Version B Version S Version Units Test Conditions/CommentsSAMPLE-A ..
5962-9152802MXA ,Low Power Quint 2-Input OR/NOR GateMILITARY DATA SHEETOriginal Creation Date: 10/30/95MN100302-X REV 1A0Last Update Date: 08/28/96Last ..
5962-9152802MYA ,Low Power Quint 2-Input OR/NOR GateGeneral DescriptionThe 100302 is a monolithic quint 2-input OR/NOR gate with common Enable. All in ..
5962-9153001MXA ,Low Power Hex TTL-to-ECL TranslatorGeneral DescriptionThe 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL ..
744766220 , SMD-RF-Choke WE-GF
744766220 , SMD-RF-Choke WE-GF
744770015 , POWER-CHOKE WE-PD
74477007 , POWER-CHOKE WE-PD
744770112 , POWER-CHOKE WE-PD
74477110 , POWER-CHOKE WE-PD
5962-9091001MRA
Octal D Flip-Flop with Clock Enable
TL/F/9525
54F/74F377
Octal
Flip-Flop
with
Clock
Enable
May 1995
54F/74F377
OctalD Flip-Flop with Clock Enable
General Description
The ’F377 has eight edge-triggered, D-type flip-flops with
individualD inputs andQ outputs. The common buffered
Clock(CP) input loadsall flip-flopssimultaneously, whenthe
Clock Enable (CE)is LOW.
The registeris fully edge-triggered.The stateof eachDin-
put, one setup time beforethe LOW-to-HIGH clock tran-
sition,is transferredtothe corresponding flip-flop’sQout-
put.TheCE input mustbe stable onlyone setup time priorthe LOW-to-HIGH clock transitionfor predictable opera-
tion.
Features Idealfor addressable register applications Clock enablefor addressand data synchronization
applications Eight edge-triggeredD flip-flops Buffered common clock See ’F273for master reset version See ’F373for transparent latch version See ’F374for TRI-STATEÉ version Guaranteed 4000V minimum ESD protection
Commercial Military Package PackageDescriptionNumber
74F377PC N20A 20-Lead(0.300× Wide) Molded Dual-In-Line
54F377DM(QB) J20A 20-LeadCeramic Dual-In-Line
74F377SC (Note1) M20B 20-Lead(0.300× Wide) Molded Small Outline, JEDEC
74F377SJ(Note1) M20D 20-Lead(0.300× Wide) Molded Small Outline, EIAJ
54F377FM (QB) W20A 20-LeadCerpack
54F377LM(QB) E20A 20-LeadCeramic Leadless ChipCarrier, TypeC
Note1: Devicesalso availablein13×reel.Usesuffixe SCXandSJX.
Logic Symbols
TL/F/9525–1
IEEE/IEC
TL/F/9525–4
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M75/PrintedinU.S.A.
