100336 ,Low Power 4-Stage Counter/Shift Registerapplications. A HIGH signal onter or as a 4-bit bidirectional shift register. Three Select (S ) the ..
100336DC , Low Power 4-Stage Counter/Shift RegisterGeneral Descriptionor to preset the counter in programmable counter applica-The 100336 operates as ..
100336PC ,Low Power 4-Stage Counter/Shift RegisterGeneral Descriptionor to preset the counter in programmable counter applica-The 100336 operates as ..
100336QC ,Low Power 4-Stage Counter/Shift RegisterGeneral Descriptionor to preset the counter in programmable counter applica-The 100336 operates as ..
100336QC ,Low Power 4-Stage Counter/Shift RegisterGeneral Descriptionor to preset the counter in programmable counter applica-The 100336 operates as ..
100336QC ,Low Power 4-Stage Counter/Shift Register100336 Low Power 4-Stage Counter/Shift RegisterAugust 1989Revised August 2000100336Low Power 4-Stag ..
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100336
Low Power 4-Stage Counter/Shift Register
TL/F/10584
Low
Power
4-Stage
Counter/Shift
Register
July 1992
Low Power 4-Stage Counter/Shift Register
General Description
The 100336operatesas eithera modulo-16 up/down coun-
terorasa 4-bit bidirectional shift register. Three Select(Sn)
inputs determinethe modeof operation,as showninthe
Function Select table. Two Count Enable (CEP, CET) inputs
are providedfor easeof cascadingin multistage counters.
One CountEnable (CET) input alsodoublesas aSerial Data
(D0) inputfor shift-up operation.For shift-down operation,isthe Serial Data input.In counting operations theTermi-
nal Count (TC) output goes LOW whenthe counter reachesinthe count/up modeor0 (zero)inthe count/down
mode.Inthe shift modes,theTC output repeatstheQ3
output.The dual natureofthis TC/Q3 outputandtheD0/
CET input meansthat one interconnection from one stagethe next higher stage servesasthelinkfor multistage
countingor shift-up operation.The individual Preset (Pn)in-
putsare usedto enter datain parallelorto presetthe coun-
terin programmable counter applications.A HIGH signalon
the Master Reset (MR) input overridesall other inputsand
asynchronously clearsthe flip-flops.In addition,a synchro-
nous clearis provided,as wellasa complement function
which synchronously invertsthe contentsofthe flip-flops.
All inputs have50kX pull-down resistors.
Features 40% power reductionofthe 100136 2000V ESD protection Pin/function compatible with 100136 Voltage compensated operating rangee
b4.2Vto b5.7V Availableto industrial grade temperature range Availableto MIL-STD-883
Logic Symbol
TL/F/10584–1
Pin Names Description ClockPulseInput
CEP CountEnable Parallel Input (Active LOW)
D0/CET SerialData Input/CountEnable
Trickle Input (Active LOW)
S0–S2 SelectInputs MasterResetInput
P0–P3 Preset Inputs SerialData Input Terminal Count Output
Q0–Q3 Data Outputs
Q0–Q3 Complementary DataOutputs
Connection Diagrams
24-Pin DIP/SOIC
TL/F/10584–2
28-PinPCC
TL/F/10584–4
24-Pin QuadCerpak
TL/F/10584–3
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
