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TDA7309D013TR
DIGITAL CONTROLLED STEREO AUDIO PROCESSOR WITH LOUDNESS
TDA7309DIGITAL CONTROLLED STEREO AUDIO PROCESSOR
WITH LOUDNESS
INPUT MULTIPLEXER:
3 STEREO INPUTS
RECORD OUTPUT FUNCTION
LOUDNESS FUNCTION
VOLUME CONTROL IN 1dB STEPS
INDEPENDENT LEFT AND RIGHT VOLUME
CONTROL
SOFT MUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL I2 C BUS
DESCRIPTIONThe TDA7309 is a control processor with inde-
pendent left and right volume control for quality
audio applications. Selectable external loudness
and soft mute functions are provided.
Control is accomplished by serial I2C bus micro-
processor interface.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise and Low DC stepping
are obtained.
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
QUICK REFERENCE DATA
PIN CONNECTION (Top View)
TEST CIRCUIT
TDA73092/12
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Tamb = 25°C, VS = 9V, RL = 10KΩ,RG = 50Ω, all controls flat (G = 0), f = 1KHz unless otherwise specified.)
SUPPLY
INPUT SELECTORS
VOLUME CONTROL
SOFT MUTE
AUDIO OUTPUTS
GENERAL
BUS INPUTS
(*) Hedevice work until 5V but no guarantee about SVR
THERMAL DATA
TDA73093/12
Figure 1: Noise vs. volume setting.
Figure 3: THD vs. frequency
Figure 5: Channel separation vs. frequency.
Figure 4: THD vs. RLOAD.
Figure 6: Output clip level vs. Supply Voltage.
Figure 2: SVRR vs. frequency.
TDA73094/12
Figure 7: Quiescent current vs. supply voltage.
Figure 9: Loudnes vs. Frequency(CLOUD = 100nF) vs. Volume
Figure 10: Loudness vs. External Capacitors
Figure 8: Loudness vs. Volume Attenuation.
TDA73095/12
2 C BUS INTERFACEData transmission from microprocessor to the
TDA7313 and viceversa takes place thru the 2
wires I2 C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).
Data ValidityAs shown in fig. 11, the data on the SDA line
must be stable during the high period of the clock.
The HIGH and LOW state of the data line can
only change when the clock signal on the SCL
line is LOW.
Start and Stop ConditionsAs shown in fig. 12 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Byte FormatEvery byte transferred on the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
AcknowledgeThe master (μP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 13). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without AcknowledgeAvoiding to detect the acknowledge of the audio-
processor, the μP can use a simplier transmis-
sion: simply it waits one clock without checking
the slave acknowledging, and sends the new
data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Figure 11: Data Validity on the I2 CBUS
Figure 12: Timing Diagram of I2 CBUS
Figure 13: Acknowledge on the I2 CBUS
TDA73096/12
