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TDA7563PD ,MULTIFUNCTION QUAD POWER AMPLIFIER WITH BUILT-IN DIAGNOSTICS FEATURESFEATURESFigure 1. Package■ MULTIPOWER BCD TECHNOLOGY■ MOSFET OUTPUT POWER STAGE■ DMOS POWER OUTPUT■ ..
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TC9452F
SINGLE CHIP SURROUND LSI
TOSHIBA
TC9452F
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC9452F
SINGLE CHIP SURROUND LSI
TC9452F is single chip Surround LSI for portable
equipment, Mini compo.
As built-in ADC/DAC, Surround, Digital equalizer,
compressor, bass treble and stereo wide, this IC constructs
DSP function.
FEATURES
0 Built-in 3channel AD converter.
THD 2 -65dB S/N I 78dB (typ.)
Built-in Ope Amp for Pre-filter. QFP44-P-1414-0.80D
o Built-in 2channel DA converter.
THD : -85dB S/N .' 93dB (typ.)
Built-in 3rd Analog filter.
Weight : 1.07g (Typ.)
0 Input : 3 Analog channel, 1 Digitel stereo port.
Digital Input format .' MSB first 16, 18, 20bit effective data before change point of LRCK or Ps.
It Output .' 2 Analog Output/1 Digitel stereo port.
Digital Output format : MSB first 16, 20bit effective data before change point of LRCK or PS.
a Built-in 64Kbit delay RAM.
0 DSP function
Surround
Compressor or Bass boost
2 Band Parametric Equalizer
Stereo wide
Pseudo stereo
Mic echo
Vocal cancel
It Package is OFF 44pins.
: Real Surround to use delay, simulate sound field of Hole,
Church, Stadium and etc.
: Dynamic Surround to respond an input
: Equalizer of a high precision of 18bit coefficient
: Emphasis of stereo source
: Like a stereo of monorail source
: 1 of 3 ADC inputs is used for this function
:Suppress vocal signal from stereo source
1 2001-06-19
BLOCK DIAGRAM/APPLICATION CIRCUIT
TA2011S
MIC amplifier MICOM
EITUEIE
TOSHIBA
13533 /rip,
dilily
It-ity
MIC IN '
MICI MICOM IIF
6 I :, 1 Delay RAM J
MicTHRU l ‘ I r\
CD. LD, MD, etc
BCKI Processor
I " <4 Sch I
Analog input LINE L-ch IN AIL
Tape, Tuner, 5
LD (FM). etc DATA
Digital Output
Anmher
DSP, DAC. etc
Timing Gene. H
2th 2256/384
I os12/7sa l. ______________
1/2 “S '-
DAC MCK2 :
Mic THRU ©—l
L-(h OUT
R-ch OUT
Analog OUTPUT
TC9452F - 2
TC9452F
TOSHIBA TC9452F
TERMINAL DESCRIPTION
No. TERMINAL IO FUNCTION REMARK
1 VDA1 - ADC Voltage supply terminal.
2 MICI I MIC LPF input terminal.
3 LPFO1 O MIC LPF output terminal.
4 VRA1 - ADC reference voltage terminal.
5 AIL I LPF input terminal for L-ch Line input.
6 LPF02 O LPF output terminal for L-ch Line input.
7 VRA2 - ADC reference voltage terminal.
8 AIR I LPF input terminal for R-ch Line input.
9 LPFO3 O LPF output terminal for L-ch Line input.
10 GNDA1 - ADC GND terminal.
11 LI I L-ch Analog additional input terminal.
(When not using : OPEN)
12 L2 0 L-ch Digital input 0 detect terminal.
13 GNDA2 - DAC GND terminal.
14 AOL O L-ch DAC output terminal.
15 VR2 - DAC reference voltage terminal.
16 AOR O R-ch DAC output terminal.
17 VDA2 - DAC voltage supply terminal.
18 R2 0 R-ch Digital input 0 detect terminal.
19 RI I R-ch Analog additional input terminal.
(When not using : OPEN)
20 VDX - Crystal oscillator voltage supply terminal.
21 XI I Crystal oscillator connection terminal.
(256, 384, 512, 768fs)
22 XO 0 Crystal oscillator connection terminal.
23 GNDX - Crystal oscillator GND terminal.
24 VDD1 - Digital voltage supply terminal.
Master clock select terminal.
25 CKS I CH'' : 256/384fs, "L" : 512/768fs)
26 MCK2 O 1/2 divider clock output terminal.
27 MCK1 O Oscillator clock output terminal.
28 SDO 0 Digital Audio Data output terminal.
29 BCKO 0 Bit clock output terminal.
30 LRCKO 0 Channel clock output terminal.
31 SDI I Digital Audio Data input terminal.
32 BCKI I Bit clock input terminal.
33 LRCKI I Channel clock input terminal.
34 GNDD - Digital GND terminal.
35 RESET I Reset terminal. ("L" Reset active) pull-up resister
36 IFD I p-COM I/F data input terminal.
37 IFS I p-COM l/F data shift clock input terminal.
38 IFL I p-COM l/F latch pulse input terminal.
2001 -06-1 9
TOSHIBA TC9452F
No. TERMINAL I/O FUNCTION REMARK
De-emphasis filter setting terminal.
39 EMP I ("H" : De-emphasis filter ON)
40 EXTO O Extend output terminal.
41 TEST I Test terminal. Usually "H" pull-up resister
42 VDD2 - Digital Voltage supply terminal.
43 VDL - Digital Voltage supply terminal for DRAM.
44 GNDL - Digital GND terminal for DRAM.
Block operating description
1. Operating Clock
Master clock (Input or oscillating XI terminal) is 768/512/384/256fs. These mode are selected by
CKS terminal, and 256fs or 384fs, 768fs or 512fs select is auto detect by this IC.
But following internal synchronize mode can not use 384/768fs, can only use 256/512fs.
And DSP calculate steps don't concern master clock, but DA converter operating clock change by
master clock. DAC is 2-n modulation method and operates oversampling, If 256fs is selected,
Oversampling ratio is 128fs and so became worse S/N, THD+N.
Table.1-1 Master clock select and DAC oversampling ratio.
CKS MASTER CLOCK DAC OVERSAMPLING RATIO
L 768fs 192fs
512fs 256fs
H 384fs 192fs
256fs 128fs
2. Digital Audio Input/Output
Synchronize mode
Data input/output Bit clock is selected internal synchronize or external synchronize by
"SYNMI", "SYNM2". (p-COM I/F bit)
Table.2-1-1 Synchronize mode and Input/Output Bit clock.
SYNM2 SYNM1 SYNCHRONIZE BCKI BCKO
0 0 internal (*) 64fs (**)
0 1 external 32fs BCKI
1 0 external 48fs BCKI
1 1 external 64fs BCKI
(*) Table 2-2-1 shown.
(**) Internal clock divider.
2001 -06-1 9
TOSHIBA
TC9452F
Input/Output channel clock (LRCKI, LRCKO) data is selected by p-COM I/F. (RLS bit)
Table.2-1-2 Channel clock
OPERATE
LRCKI, LRCKO : "H" Level, L-ch data input/output
LRCKI, LRCKO : "L" Level, L-ch data input/output
2.2 Data Input format
Data input format is Table.2-2-1 and Fig.1.
Selecting use IBIT1 and IBIT2. (p-COM I/F)
Table.2-2-1 Data input format
SYNM2 SYNM1 IBIT2 IBIT1 FORMAT BCKI
o o o o _J§ MSBfirst 16bit 32fs--128fs
o o o 1 2‘3 MSBfirst 18bit 36fs--128fs
o o 1 o 35 MSBfirst 20bit 40fs--128fs
0 0 1 1 -2-, HS MAX20bit 64fs only
0 1 0 0 MSBfirst 16bit 32fs
O 1 0 1 Lu not use 32fs
0 1 1 0 !i) not use 32fs
0 1 1 1 0 not use 32fs
a: . .
1 0 0 O 5 MSBfirst 16bit 48fs
1 0 0 1 , MSBfirst 18bit 48fs
1 0 1 0 C' MSBfirst 20bit 48fs
1 0 1 1 g not use 48fs
1 1 0 0 E MSBfirst 16bit 64fs
1 1 o 1 Q MSBfirst 18bit 64fs
1 1 1 0 MSBfirst 20bit 64fs
1 1 1 1 HS MAX20bit 64fs
5 2001-06-19
TOSHIBA TC9452F
L-(h R-(h
1300 WWWWWW
mm = "L" 15112 = "L" : 2 3
SDI IIIEIII CEEEEEETEEEEE1Tr1 CrITr:TTErrrrrEED
MSB LSD ;
IBtT1='H'H8IT2='L'' 1 '
SOI ITrmTrrrrrrrrrm rzr1zr1"zrrr1z1zrl,
M55 Isis
18111: "L' I8IT2-- "H"
SDI a:I:ma:Em:ma:ma:Ei rzszmzzazzmaaaaza::'
IBIT1= 'H"|BITZ ="H" MSB "53
SOI '::crrrrrrrrrrrrrrazzm :_'tzEErCrrrraTEEITEEITo , CEITrITIT
Fig.1 Example Data input timing (RLS="H", SYNM1="H", SYNM2 ="H")
2.3 Digital Zero detect function
Table.2-3-1 Digital Zero detect judge time
fs 32kHz 44.1kHz 48kHz
Judge Time 1024ms 743ms 683ms
2.4 Stereo/Mono setting
This IC can input Double music source by "MONO", "CHS" bit. (p-COM I/F)
And this IC can input Double music source by software coefficient, too. Please show Program manual.
Table.2-4-1 Stereo/Mono setting
MONO CHS STEREO/MONO
0 0 stereo
0 1 ZERO Detect not use CL'' output only)
1 0 L-ch (CH1) MONO OUTPUT
1 1 R-ch (CH2) MONO OUTPUT
2.5 Data output formats
Table.2-5-1 Data Output formats
SYNM2 SYNM1 OBITZ OBIT1 FORMAT BCKO
o o o o -y'alre' MSBfirst 16bit 64fs
o o o 1 ietj,5, MSBfirst 20bit 64fs
o o 1 o Fei5 us 16bit 64fs
o o 1 1 Ct us 20bit 64fs
0 1 0 0 MSBfirst 16bit 32fs ( = BCKI)
0 1 0 1 m not use 32fs(=BCKI)
0 1 1 0 'i-l IIS 16bit 32fs(=BCKI)
O 1 1 1 2 not use 32fs(=BCKl)
1 0 0 0 6 MSBfirst 16bit 48fs(=BCKl)
1 0 O 1 , MSBfirst 20bit 48fs(=BCKI)
1 o 1 0 l' M 16bit 48f5(=BCKI)
1 O 1 1 g IIS 20bit 48f$(=BCKI)
1 1 0 o E MSBfirst 16bit 64fs(=BCKl)
1 1 o 1 5 MSBfirst 20bit 64fs(=BCK1)
1 1 1 0 " 16bit 64fs ( = BCKI)
1 1 1 1 HS 20bit 64fs(= BCKI)
TCMS2F-6
6 2001-06-19
TOSHIBA TC9452F
" R-ch
Jcko"-
BCKO WWWWWWWW
OEIT1="L" OBITZ: "L" , 3 _
SDOIIIIIIIEI EEEIEEDIIIEIIEI CrrrrrrrrmTr1z1
M58 LS8
OBIY1=‘H' OBITlu'L' :
Sh) tTCrrrrr1Trrrrrrrrrm CrrrrrrrrrrrrrrIrrm
M59 LSil
081T1a'L' OBITZ='H" :
SCK) . DIDIUIIIEEEEEI a LE1TEEmTEEEEEE1 CITEEEEEE
OBIT1=‘H' OBITZ='H" P" LSi1 E g
soo i, CTTErITEEEmTrE1:ITE1 2 5 CmTEEEE
MSB L58
Fig.2 Example Data Output Timing (RLS="H", SYNMI="H", SYNM2= "H")
3. p-COM l/F
3.1 Setting
p-COM l/F setting is 4 Items.
Command is variable length 16-26bits. (effective data before change point Latch pulse)
When command is 8bits unit, setting is LSB first.
All this iC’s setting change at internal program cycle beginning, but without digital attenuator setting, please mute
output signal at changing program setting.
So Coefficient setting and offset RAM writing is one word at a fs.
When many word change, please by careful.
Table.3-1-1 p-COM I/F setting
MODE FUNC. ATT. CRAM
D25 0 O 0 1
D24 0 0 1 ADS
D23 1 1 AL13 ADS
D22 0 1 AL12 AD4
D21 CHS EMS AL11 AD3
D20 MONO EM2 AL10 AD2
D19 OBITZ EMI AL09 AD1
D18 OBIT1 CEF2 AL08 ADO Me
D17 IBITZ CEF1 AL07 DT17
D16 IBIT1 CTDW ALOS DT16
D15 SYNM2 CTUP AL05 DT15
D14 SYNM1 MUTE AL04 DT14
D13 RLS EXTO ALO3 DT13
D12 LSM BB AL02 DT12
D11 RESERVED DF2 AL01 DT11
D10 ADPD DFI ALOO DT10 Lbyte
D09 - - - DT09
D08 - - - DT08
D07 - - - DT07
D06 - - - DT06
D05 - - - DT05
D04 - - - DT04
D03 - - - DT03
D02 - - - DT02 Me
DOI - - - DT01
DOD - - - DTOO
TC9452F - 7
7 2001-06-19
TOSHIBA TC9452F
(a) Digital Attenuator (16bit command)
IFS U ..... I I I I I I I i : I I I I I I I I 5
1 I I 1
l t t ':
IFD don't care X ALOO X AL01 x I l X AL12 X AL13 X 1 N 0 ‘ don't care
IIIII : I ,' :
IFL , .i-s
i Valid data (16bit) J
(b)Coefficient offset RAM writing (26bit command)
'FS-I-I- ..... iriirril!'
IFD don't care X DTOO X DT01 x I
X W x AD5 x AD6 X 1 x don'tcare
IFL 5 i I
. Valid data (26bit) .
Fig.3 Example p-COM l/F
8 2001-06-19
TOSHIBA TC9452F
3.2 Operating mode setting [MODE]
Please set these mode at voltage supply.
When RESET is "L", these data is clear.
ADPD : ADC power down (H : power down)
RESERVED : "L"
LSM : Digital Attenuator soft mute time select CH'' :twice)
RLS .' Channel clock select (H .' LRCK="L" is L-ch data)
SYNM1, 2 .' DATA input/output synchronize clock select
IBIT1, 2 : Input DATA format select
OBIT1, 2 : Output DATA format select
MONO : MONO DATA input select
CHS : At MONO Setting, channel select, At stereo setting, zero detect setting
3.3 DSP setting [FUNC]
At RESET terminal is "L" level, these data is clear.
DF1, 2 , SFC, Mic echo desimetion ratio select
BB : Compressor/Bass Boost filter select ("H" : Bass Boost filter)
EXTO : Expand output terminal OUTPUT DATA
MUTE .' OUTPUT mute CH'' : mute, ATT setting is hold)
CTUP : Compressor attack time select
CTDW : Compressor release time select
CEF1 : Compressor/Bass Boost select CH'' : Bass Boost)
CEF2 : Compressor/Bass Boost effect select CH'' : Large effect)
EM1, 2 : De-emphasis filter select
EMS : De-emphasis filter block select
Table.3-3-1 De-emphasis setting
TERMINAL l/F SETTING
EMP EMS EM2 EM1 FUNCTION
0 0 - - OFF
1 0 0 0 de-emphasis 1 44.1kHz
1 o o 1 DIGITAL INPUT OFF
1 0 1 0 de-emphasis 1 48kHz
1 0 1 1 de-emphasis 1 32kHz
0 1 - - OFF
1 1 0 0 de-emphasis 2 44.1kHz
1 1 o 1 DAC DF OFF
1 1 1 0 de-emphasis 2 48kHz
1 1 1 1 de-emphasis 2 32kHz
9 2001-06-19
TOSHIBA TC9452F
3.4 Digital Attenuator Setting [ATT]
Table.3-4-1 Digital Attenuator level setting
AL [13 : 00] OUTPUT LEVEL
3FFFH - 0.000dB .
3FFDH -0.001dB [Level S.Ettm] * A
3FFBH -0.002dB AL [13 . 00] =3FFFH 10 (LEVEL/20)
2D4EH - 3.000dB
2013H - 6.000dB
0002H - 78.268dB
0001 H - 84.288dB
0000H - codB
Table.3-4-2 Digital Attenuator mute time
LSM 32kHz 44.1kHz 48kHz
0 32ms 23ms 21ms
1 64ms 46ms 42ms
OdB (3FFFH) ---cxadB (0000H) Changing Time
3.5 Coefficient, Offset RAM writing [CRAM]
Coefficient and offset RAM writing operate one word at a fs.
RAM is 128wordx18bit.
Delay RAM Address offset data format is as follows.
Detail setting, please show soft ware manual.
DT17 16 15 14 13 12 11 IO 09 08 07 06 05 04 03 02 01 oo
l2l1l0l2l1liol11l10l09l08l07l06l0slio4lio3l02lio1l00l
MAL I DECI I DLOF I
MAL [2:0] : Delay RAM setting select
DECI [2:0] : Decimation ratio select
DLOF [11 :00] : Offset Address select
Fig.4 Coefficient, Offset RAM, Offset Address Setting
10 2001-06-19
TOSHIBA
AD converter
TC9452F
Built-in Line input L-ch and R-ch AD converter, and Mic signal input AD converter.
Mic input signal convert Digital signal and DSP
make digital echo signal.
Mic signal add this echo signal by LI, RI terminal or external Op-amp.
It is necessary to open LI and RI terminal at the using Op-amp.
When not using AD converter, please short-circuit interval each terminal MICI-LPFO1, AIL-LPFO2 and
AIR-LPFO3
DA converter
This is E-n modulation 1bit DA converter.
Built-in Trd Analog Filter.
It is possible to add analog through signal (LI and RI terminal) at the output portion of DAC.
6. Timing
6.1 Reset Timing
At power supply, please set RESET terminal "L'' level at one time.
Power ON Reset Timing is as follows.
Fig.5 Power on Reset Timing
6.2 p-COM l/F Timing
T3, T4, T6 :
iu-Trc.s- Ts-d.
: Setup time>1ps
: Hold time>lps
Clock pulse width>1/zs
: Hold time>lps
Fig.6 p-COM I/F Timing
2001 -06-1 9
TOSHIBA TC9452F
MAXIMUM RATINGS
CHARACTERISTIC SYMBOL RATING UNIT
Supply Voltage VDD -0.r-6.0 V
Input Voltage Vin -0.r-VDD+0.3 V
Power Dissipation PD 500 mW
Operating Temperature Topr -40--85 "C
Storage Temperature Tstg - 55-150 "C
ELECTRICAL CHARACTERISTICS (DC)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Operating Supply Voltage VDD - Ta = -40--85oc 4.5 5.0 5.5 V
Power Supply Current IDD - Xl=16SMHz, Output No-Ioad - 48 70 mA
"H" Level VIH :9ng - VDD
Input Voltage - Digital input terminal . V V
" " - DD
L Level " 0 x 0.2
"H" Level IIH . . . . - - 1.0
In t C rrent - D tal n t term nal
pu u "L" Level IIL 'g' I pu I - 1.0 - - pA
"H" L I I - . -
Output Current 1 " " eve OHI - LRCKO, BCKO, SDO 3 5 mA
L Level IOL1 - - 2.0
"H" L I I - . -
Output Current 2 " " eve 0H2 - MCK1, MCK2 5 0 mA
L Level IOLZ - - 3.0
Output Current 3 "H" Level IOH3 - EXTO -2.0 - mA
L Level IOL3 - - 2.0
Pull-up Resistance RUP - RESET, TEST - 50 - k0
2001 -06-1 9
TOSHIBA TC9452F
ELECTRICAL CHARACTERISTICS (AC)
AD converter
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Maximum Input Level Ain - vDD=5.ov - 1.1 - vrms
. -30di? 1kHz
S/(N+D) Ratio S/N(AD) - Sine wave input (*) 68 78 - dB
Total. Harmonic Distortion THD (AD) - _-.0dhs Ikriz - - 65 - 55 dB
+Noise Sine wave input
Cross-talk CT(AD) - - - -68 -60 dB
(*) A-Weight : ON (Typ.)
DA converter
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Output Level Aout - - - 1.2 - Vrms
S/N Ratio S/N(DA) - TOdB Ikriz 87 93 - dB
Sine wave input
-0dB 1kHz
Total Harmonic Distortion THD1 (DA) Sine wave input - -83 -78 dB
N . - -
+ olse THD2(DA) .OdB 10k.HZ - -83 -75
Sine wave input
Cross-talk CT(DA) - - - -88 -83 dB
13 2001-06-19
TOSHIBA TC9452F
Timing
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
. . - LRCKO, BCKO, SDO, EXTO - - 15
Rise Time tr - MCK1, MCK2 - - 8
. - LRCKO, BCKO, SDO, EXTO - - 15
Fall Time tf - MCK1, MCK2 - - 8
- LRCKI-9LRCKO - - 30
(External clock synchronous)
- BCKl-yBCKO - - 20 ns
(External clock synchronous)
Delay Time td - BCKO-9SDO - - 10
- MCK1-9LRCKO - - 50
(Internal clock synchronous)
- MCKI-9BCKO - - 20
(Internal clock synchronous)
XI=256fs 8.0 11.3 12.5
Operating Frequency fopr - XI=384fs 10.0 16.9 18.5 MHz
Xl=512fs 16.0 22.6 25.5
XI = 768fs 24.0 33.9 34.0
(Note 1) At the external clock synchronous, LRCKO and BCKO output signal are same as
LRCKI and BCKI input signal.
At the internal clock synchronous, LRCKO and BCKO output signal are output
synchronously with the falling edge of MCK1.
(Note 2) Measured with the output load CL=10pF.
(Note 3) At the XI clock is 256fs, 384fs and 512fs, it is operated with the fs=32kHz,
44.1kHz and 48kHz. At the XI clock is 768fs, it is operated with the fs=32kHz and
44.1kHz.
(Note 4) Delay RAM applications has limitations with the how to control the DRAM. Show
the software manual.
AC CHARACTERISTIC POINT (Input signal : LRCK, BCK, DATA)
BCK -y/'-vs
2001 -06-1 9
TOSHIBA TC9452F
PACKAGE DIMENSIONS
QFP44-P-1414-0.80D Unit : mm
18.9i0.3
14.0i0.2
3.0TYP
m tiiTululululu3t-
o-ie eo"
1 .352t0.2
Weight : 1.07g (Typ.)
15 2001-06-19
TOSHIBA TC9452F
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
16 2001-06-19
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