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STTS2002B2DN3F
2.3 V memory module temperature sensor with a 2 Kb SPD EEPROM
March 2011 Doc ID 15389 Rev 5 1/52
STTS20022.3 V memory module temperature sensor
with a 2 Kb SPD EEPROM
Features 2.3 V memory module temperature sensor with
integrated 2 Kb SPD EEPROM Forward compatible with JEDEC TSE 2002a2
and backward compatible with STTS424E02 Operating temperature range: –40 °C to +125 °C Single supply voltage: 2.3 V to 3.6 V 2 mm x 3 mm TDFN8, height: 0.80 mm (max) JEDEC MO-229, WCED-3 compliant RoHS compliant, halogen-free
Temperature sensor Temperature sensor resolution:
programmable (9-12 bits)
0.25 °C (typ)/LSB - (10-bit) default Temperature sensor accuracy (max): ± 1 °C from +75 °C to +95 °C ± 2 °C from +40 °C to +125 °C ± 3 °C from –40 °C to +125 °C ADC conversion time: 125 ms (max) at default
resolution (10-bit) Typical operating supply current: 160 µA
(EEPROM standby) Temperature hysteresis selectable set points
from: 0, 1.5, 3, 6.0 °C Supports SMBus timeout 25 ms - 35 ms
2 Kb SPD EEPROM Functionality identical to ST’s M34E02 SPD
EEPROM Permanent and reversible software data
protection for the lower 128 bytes Byte and page write (up to 16 bytes) Self-time WRITE cycle (5 ms, max) Automatic address incrementing
Two-wire bus Two-wire SMBus/I2 C - compatible serial
interface Supports up to 400 kHz transfer rate Does not initiate clock stretching
Contents STTS20022/52 Doc ID 15389 Rev 5
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Serial communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1 Device type identifier (DTI) code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 A0, A1, A2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.2 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.3 SDA (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.4 SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.5 EVENT (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.6 VDD (power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Temperature sensor operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.1 SMBus/I2 C communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 SMBus/I2 C slave sub-address decoding . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 SMBus/I2 C AC timing consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Temperature sensor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164.1 Capability register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 Configuration register (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.1 Event thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.2 Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.3 Comparator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.4 Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.5 Event output pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3 T emperature register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3.1 Temperature format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4 T emperature trip point registers (read/write) . . . . . . . . . . . . . . . . . . . . . . 25
4.4.1 Alarm window trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.4.2 Critical trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.5 Manufacturer ID register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.6 Device ID and device revision ID register (read-only) . . . . . . . . . . . . . . . 28
4.7 T emperature resolution register (read/write) . . . . . . . . . . . . . . . . . . . . . . 29
STTS2002 ContentsDoc ID 15389 Rev 5 3/52
4.8 SMBus timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SPD EEPROM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305.1 2 Kb SPD EEPROM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2 Internal device reset - SPD EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.4 Software write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.4.1 SWP and CWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.4.2 PSWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.5 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.5.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.5.2 Page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.5.3 Write cycle polling using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.6 Read operations - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.6.1 Random address read - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.6.2 Current address read - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.6.3 Sequential read - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.6.4 Acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.7 Initial delivery state - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Use in a memory module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396.1 Programming the SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.1.1 DIMM isolated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.1.2 DIMM inserted in the application motherboard . . . . . . . . . . . . . . . . . . . 39
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
List of tables STTS2002
4/52 Doc ID 15389 Rev 5
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. AC characteristics of STTS2002 for SMBus and I2 C compatibility timings. . . . . . . . . . . . . 15
Table 3. Temperature sensor registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Pointer register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Pointer register select bits (type, width, and default values). . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Capability register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. Capability register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Configuration register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9. Configuration register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Hysteresis as applied to temperature movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11. Legend for Figure 9: Event output boundary timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12. Temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 13. Temperature register coding examples (for 10 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14. Temperature register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 15. Temperature trip point register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. Alarm temperature upper boundary register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 17. Alarm temperature lower boundary register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 18. Critical temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 19. Manufacturer ID register (read-only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 20. Device ID and device revision ID register (read-only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 21. Temperature resolution register (TRES) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 22. TRES details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 23. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 24. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 25. Acknowledge when writing data or defining the write-protection (instructions with R/W bit =
0)37
Table 26. Acknowledge when reading the write protection (instructions with R/W bit=1). . . . . . . . . . 38
Table 27. DRAM DIMM connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 28. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 29. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 30. DC/AC characteristics - temperature sensor component with EEPROM . . . . . . . . . . . . . . 41
Table 31. TDFN8 – 8-lead thin dual flat, no-lead (2 mm x 3 mm) mechanical data (DN) . . . . . . . . . . 44
Table 32. Parameters for landing pattern - TDFN8 package (DN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 33. Carrier tape dimensions TDFN8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 34. Reel dimensions for 8 mm carrier tape - TDFN8 package . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 35. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 36. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
STTS2002 List of figures
Doc ID 15389 Rev 5 5/52
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. TDFN8 connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. SMBus/I2C write to pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. SMBus/I2 C write to pointer register, followed by a read data word. . . . . . . . . . . . . . . . . . . 12
Figure 6. SMBus/I2 C write to pointer register, followed by a write data word . . . . . . . . . . . . . . . . . . 13
Figure 7. SMBus/I2 C timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9. Event output boundary timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10. Result of setting the write protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 11. Setting the write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 12. Write mode sequences in a non write-protected area of SPD . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 14. Read mode sequences - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 15. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 16. TDFN8 – 8-lead thin dual flat, no-lead (2 mm x 3 mm) package outline (DN) . . . . . . . . . . 44
Figure 17. DN package topside marking information (TDFN8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 18. Landing pattern - TDFN8 package (DN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 19. Carrier tape for TDFN8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 20. Reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Description STTS2002
6/52 Doc ID 15389 Rev 5
1 Description
The STTS2002 is targeted for DIMM modules in mobile personal computing platforms
(laptops), servers and other industrial applications. The thermal sensor (TS) in the
STTS2002 is compliant with the JEDEC specification TSE2002a2, which defines memory
module thermal sensors requirements for mobile platforms. The 2 Kb serial presence detect
(SPD) I2 C-compatible electrically erasable programmable memory (EEPROM) in the
STTS2002 is organized as 256 x8 bits and is functionally identical to the industry standard
M34E02.
The TS-SPD EEPROM combination provides space as well as cost savings for mobile and
server platform dual inline memory modules (DIMM) manufacturers, as it is packaged in the
compact 2 mm x 3 mm 8-lead TDFN package with a thinner maximum height of 0.80 mm.
The DN package is compliant to JEDEC MO-229, variation WCED-3.
The digital temperature sensor has a programmable 9-12 bit analog-to-digital converter
(ADC) which monitors and digitizes the temperature to a resolution of up to 0.0625 °C. The
default resolution is 0.25 °C/LSB (10-bit). The typical accuracies over these temperature
ranges are:
±2 °C over the full temperature measurement range of –40 °C to 125 °C
±1 °C in the +40 °C to +125 °C active temperature range, and
±0.5 °C in the +75 °C to +95 °C monitor temperature range
The temperature sensor in the STTS2002 is specified for operating at supply voltages from
2.3 V to 3.6 V. Operating at 3.3 V, the typical supply current is 160 µA (includes SMBus
communication current).
The on-board sigma delta ADC converts the measured temperature to a digital value that is
calibrated in °C. For Fahrenheit applications, a lookup table or conversion routine is
required. The STTS2002 is factory-calibrated and requires no external components to
measure temperature.
The digital temperature sensor component has user-programmable registers that provide
the capabilities for DIMM temperature-sensing applications. The open drain event output pin
is active when the monitoring temperature exceeds a programmable limit, or it falls above or
below an alarm window. The user has the option to set the event output as a critical
temperature output. This pin can be configured to operate in either a comparator mode for
thermostat operation or in interrupt mode.
The 2 Kb serial EEPROM memory in the STTS2002 has the ability to permanently lock the
data in its first half (upper) 128 bytes (locations 00h to 7Fh). This feature has been designed
specifically for use in DRAM DIMMs with SPD. All of the information concerning the DRAM
module configuration (e.g. access speed, size, and organization) can be kept write
protected in the first half of the memory. The second half (lower) 128 bytes of the memory
can be write protected using two different software write protection mechanisms.
By sending the device a specific sequence, the first 128 bytes of the memory become write
protected: permanently or resettable. In the STTS2002 the write protection of the memory
array is dependent on whether the software protection has been set.
STTS2002 Serial communications
Doc ID 15389 Rev 5 7/52
2 Serial communications
The STTS2002 has a simple 2-wire SMBus/I2 C-compatible digital serial interface which
allows the user to access both the 2 Kb serial EEPROM and the data in the temperature
register at any time. It communicates via the serial interface with a master controller which
operates at speeds of up to 400 kHz. It also gives the user easy access to all of the
STTS2002 registers in order to customize device operation.
2.1 Device type identifier (DTI) code
The JEDEC temperature sensor and EEPROM each have their own unique I2 C address,
which ensures that there are no compatibility or data translation issues. This is due to the
fact that each of the devices have their own 4-bit DTI code, while the remaining three bits
are configurable. This enables the EEPROM and thermal sensors to provide their own
individual data via their unique addresses and still not interfere with each other’s operation
in any way. The DTI codes are: '0011' for the TS, and '1010' for addressing the EEPROM memory array, and ‘0110’ to access the software write protection settings of the EEPROM.
Serial communications STTS2002
8/52 Doc ID 15389 Rev 5
Figure 1. Logic diagram SDA and EVENT are open drain.
Note: See Section 2.2: Pin descriptions on page 10 for details.
Figure 2. TDFN8 connections (top view) SDA and EVENT are open drain.
Table 1. Signal names SDA and EVENT are open drain.
STTS2002 Serial communications
Doc ID 15389 Rev 5 9/52
Figure 3. Block diagram
Serial communications STTS2002
10/52 Doc ID 15389 Rev 5
2.2 Pin descriptions
2.2.1 A0, A1, A2
A2, A1, and A0 are selectable address pins for the 3 LSBs of the I2 C interface address.
They can be set to VDD or GND to provide 8 unique address selections. These pins are
internally connected to the E2, E1, E0 (chip selects) of EEPROM.
2.2.2 VSS (ground)
This is the reference for the power supply. It must be connected to system ground.
2.2.3 SDA (open drain)
This is the serial data input/output pin.
2.2.4 SCL
This is the serial clock input pin.
2.2.5 EVENT (open drain)
This output pin is open drain and active-low.
2.2.6 VDD (power)
This is the supply voltage pin, and ranges from 2.3 V to 3.6 V.
STTS2002 Temperature sensor operation
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The temperature sensor continuously monitors the ambient temperature and updates the
temperature data register. T emperature data is latched internally by the device and may be
read by software from the bus host at any time.
The SMBus/I2 C slave address selection pins allow up to 8 such devices to co-exist on the
same bus. This means that up to 8 memory modules can be supported, given that each
module has one such slave device address slot.
After initial power-on, the configuration registers are set to the default values. The software
can write to the configuration register to set bits per the bit definitions in Section 3.1:
SMBus/I2 C communications.
For details of operation and usage of 2 Kb SPD EEPROM, refer to Section 5: SPD
EEPROM operation.
3.1 SMBus/I2 C communications
The registers in this device are selected by the pointer register. At power-up, the pointer
register is set to “00”, which is the capability register location. The pointer register latches
the last location it was set to. Each data register falls into one of three types of user
accessibility: Read-only
2. Write-only, and
3. WRITE/READ same address
A WRITE to this device will always include the address byte and the pointer byte. A WRITE
to any register other than the pointer register, requires two data bytes.
Reading this device is achieved in one of two ways: If the location latched in the pointer register is correct (most of the time it is expected
that the pointer register will point to one of the read temperature registers because that
will be the data most frequently read), then the READ can simply consist of an address
byte, followed by retrieval of the two data bytes. If the pointer register needs to be set, then an address byte, pointer byte, repeat start,
and another address byte will accomplish a READ.
The data byte transfers the MSB first. At the end of a READ, this device can accept either an
acknowledge (ACK) or no acknowledge (No ACK) status from the master. The No ACK
status is typically used as a signal for the slave that the master has read its last byte. This
device subsequently takes up to 125 ms to measure the temperature for the default
temperature resolution.
Note: STTS2002 does not initiate clock stretching which is an optional I2 C bus feature.
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Figure 4. SMBus/I2 C write to pointer register
Figure 5. SMBus/I2 C write to pointer register, followed by a read data word
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Figure 6. SMBus/I2 C write to pointer register, followed by a write data word
3.2 SMBus/I2 C slave sub-address decoding
The physical address for the TS is different than that used by the EEPROM. The TS physical
address is binary 0011A2A1A0RW, where A2, A1, and A0 are the three slave sub-
address pins, and the LSB “RW” is the READ/WRITE flag.
The EEPROM physical address is binary 1 010A2A1A0RW for the memory array and is
0110A2A1A0 RW for permanently set write protection mode.
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3.3 SMBus/I2 C AC timing consideration
In order for this device to be both SMBus- and I2 C-compatible, it complies to a subset of
each specification. The requirements which enable this device to co-exist with devices on
either an SMBus or an I2 C bus include: The SMBus minimum clock frequency is required. The SMBus timeout is maximum 35 ms (temperature sensor only).
Figure 7. SMBus/I2 C timing diagram
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Table 2. AC characteristics of STTS2002 for SMBus and I2 C compatibility timings STTS2002 will not initiate clock stretching which is an I2 C bus optional feature. Guaranteed by design and characterization, not necessarily tested. For a restart condition, or following a WRITE cycle. This parameter reflects maximum WRITE time for EEPROM. Bus timeout value supported depends on setting of TMOUT bit 6 in capability register.
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The temperature sensor component is comprised of various user-programmable registers.
These registers are required to write their corresponding addresses to the pointer register.
They can be accessed by writing to their respective addresses (see Table 3). Pointer
register bits 7 - 4 must always be written to '0' (see Table 4). This must be maintained, as not
setting these bits to '0' may keep the device from performing to specifications.
The main registers include: Capability register (read-only) Configuration register (read/write) Temperature register (read-only) Temperature trip point registers (read/write), including Alarm temperature upper boundary, Alarm temperature lower boundary, and Critical temperature. Manufacturer ID register (read-only) Device ID and device revision ID register (read-only) Temperature resolution register (TRES) (read/write)
See Table 5 on page 17 for pointer register selection bit details.
Note: Registers beyond the specified (00-08) are reserved for STMicroelectronics internal use
only, for device test modes in product manufacturing. The registers must NOT be accessed
by the user (customer) in the system application or the device may not perform according to
specifications.
Table 3. Temperature sensor registers summary
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4.1 Capability register (read-only)
This 16-bit register is read-only, and provides the TS capabilities which comply with the
minimum JEDEC TSE2002a2 specifications (see Table 6 and Table 7 on page 18). The
STTS2002 resolution is programmable via writing to pointer 08 register. The power-on
default value is 0.25 °C/LSB (10-bit).
Table 4. Pointer register format
Table 5. Pointer register select bits (type, width, and default values)
Table 6. Capability register format
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Table 7. Capability register bit definitions
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4.2 Configuration register (read/write)
The 16-bit configuration register stores various configuration modes that are used to set up
the sensor registers and configure according to application and JEDEC requirements (see able 8 on page 19 and Table 9 on page 20).
4.2.1 Event thresholds
All event thresholds use hysteresis as programmed in register address 0x01 (bits 10 through
9) to be set when they de-assert.
4.2.2 Interrupt mode
The interrupt mode allows an event to occur where software may write a '1' to the clear
event bit (bit 5) to de-assert the event Interrupt output until the next trigger condition occurs.
4.2.3 Comparator mode
Comparator mode enables the device to be used as a thermostat. READs and WRITEs on
the device registers will not affect the event output in comparator mode. The event signal will
remain asserted until temperature drops outside the range or is re-programmed to make the
current temperature “out of range”.
4.2.4 Shutdown mode
The STTS2002 features a shutdown mode which disables all power-consuming activities
(e.g. temperature sampling operations), and leaves the serial interface active. This is
selected by setting shutdown bit (bit 8) to '1'. In this mode, the devices consume the
minimum current (ISHDN), as shown in Table 30 on page 41.
Note: Bit 8 cannot be set to '1' while bits 6 and 7 (the lock bits) are set to '1'.
The device may be enabled for continuous operation by clearing bit 8 to '0'. In shutdown
mode, all registers may be read or written to. Power recycling will also clear this bit and
return the device to continuous mode as well.
Table 8. Configuration register format
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Table 9. Configuration register bit definitions
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Figure 8. Hysteresis TH = Value stored in the alarm temperature upper boundary trip register TL = Value stored in the alarm temperature lower boundary trip register HYS = Absolute value of selected hysteresis
As this device is used in DIMM (memory modules) applications, it is strongly recommended that only the active-low polarity
(default) is used. This will provide full compatibility with the STTS424E02. This is the recommended configuration for the
STTS2002. The actual incident causing the event can be determined from the read temperature register. Interrupt events can be
cleared by writing to the clear event bit (writing to this bit will have no effect on overall device functioning). Writing to this register has no effect on overall device functioning in comparator mode. When read, this bit will always
return a logic '0' result.
Table 9. Configuration register bit definitions (continued)
Table 10. Hysteresis as applied to temperature movement
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4.2.5 Event output pin functionality
The STTS2002 EVENT pin is an open drain output that requires a pull-up to VDD on the
system motherboard or integrated into the master controller. EVENT has three operating
modes, depending on configuration settings and any current out-of-limit conditions. These
modes are interrupt, comparator or critical.
In interrupt mode the EVENT pin will remain asserted until it is released by writing a ‘1’ to
the “Clear Event” bit in the status register. The value to write is independent of the EVENT
polarity bit.
In comparator mode the EVENT pin will clear itself when the error condition that caused the
pin to be asserted is removed.
In the critical mode the EVENT pin will only be asserted if the measured temperature
exceeds the critical limit. Once the pin has been asserted, it will remain asserted until the
temperature drops below the critical limit minus hysteresis. Figure 9 on page 23 illustrates
the operation of the different modes over time and temperature.
When the hysteresis bits (bits 10 and 9) are enabled, hysteresis may be used to sense
temperature movement around trigger points. For example, when using the “above alarm
window” bit (temperature register bit 14, see Table 12 on page 24) and hysteresis is set to
3 °C, as the temperature rises, bit 14 is set (bit 14 = 1). The temperature is above the alarm
window and the temperature register contains a value that is greater than the value set in
the alarm temperature upper boundary register (see Table 16 on page 26).
If the temperature decreases, bit 14 will remain set until the measured temperature is less
than or equal to the value in the alarm temperature upper boundary register minus 3 °C (see
Figure 8 on page 21 and Table 10 on page 21 for details.
Similarly, when using the “below alarm window” bit (temperature register bit 13, see Table12
on page 24) will be set to '0'. The temperature is equal to or greater than the value set in the
alarm temperature lower boundary register (see Table 17 on page 26). As the temperature
decreases, bit 13 will be set to '1' when the value in the temperature register is less than the
value in the alarm temperature lower boundary register minus 3 °C (see Figure 8 on
page 21 and Table 10 on page 21 for details.
The device will retain the previous state when entering the shutdown mode. If the device
enters the shutdown mode while the EVENT pin is low, the shutdown current will increase
due to the additional event output pull-down current.
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Figure 9. Event output boundary timings
Systems that use the active high mode for Event output must be wired point-to-point
between the STTS2002 and the sensing controller. Wire-OR configurations should not be
used with active high Event output since any device pulling the Event output signal low will
mask the other devices on the bus. Also note that the normal state of Event output in active
high mode is a ‘0’ which will constantly draw power through the pull-up resistor.
Table 11. Legend for Figure 9: Event output boundary timings
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4.3 Temperature register (read-only)
This 16-bit, read-only register stores the temperature measured by the internal band gap TS
as shown inTable 12. When reading this register, the MSBs (bit 15 to bit 8) are read first, and
then the LSBs (bit 7 to bit 0) are read. The result is the current-sensed temperature. The
data format is 2s complement with one LSB = 0.25 °C for the default resolution. The MSB
has a 128 °C resolution.
The trip status bits represent the internal temperature trip detection, and are not affected by
the status of the event or configuration bits (e.g. event output control or clear event). If
neither of the above or below values are set (i.e. both are 0), then the temperature is exactly
within the user-defined alarm window boundaries.
4.3.1 Temperature format
The 16-bit value used in the trip point set and temperature read-back registers is 2s
complement, with the LSB equal to 0.0625 °C (see Table 12). For example: a value of 019C h represents 25.75 °C,
2. a value of 07C0 h represents 124 °C, and
3. a value of 1E74 h represents –24.75 °C
All unused resolution bits are set to zero. The MSB will have a resolution of 128 °C. The
STTS2002 supports programmable resolutions (9-12 bits) which is 0.5 to 0.0625 °C/LSB.
The default is 0.25 °C/LSB (10 bits) programmable.
The upper 3 bits indicate trip status based on the current temperature, and are not affected
by the event output status.
Table 12. Temperature register format Bit 2 is LSB for default 10-bit mode. Depending on status of the resolution register, bit 1 may display 0.125 °C value. Depending on status of the resolution register, bit 0 may display 0.0625 °C value. See Table 14 for explanation.
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A 0.25 °C minimum granularity is supported in all registers. Examples of valid settings and
interpretation of temperature register bits for 10-bit (0.25 °C) default resolution are provided
in Table13.
4.4 Temperature trip point registers (read/write)
The STTS2002 alarm mode registers provide for 11-bit data in 2s compliment format. The
data provides for one LSB= 0.25 °C. All unused bits in these registers are read as '0'.
The STTS2002 has three temperature trip point registers (see Table 15): Alarm temperature upper boundary threshold (Table 16), Alarm temperature lower boundary threshold (Table 17), and Critical temperature trip point value (Table 18).
Note: If the upper or lower boundary threshold values are being altered in-system, all interrupts
should be turned off until a known state can be obtained to avoid superfluous interrupt
activity.
Table 13. Temperature register coding examples (for 10 bits)
Table 14. Temperature register bit definitions
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4.4.1 Alarm window trip
The device provides a comparison window with an upper temperature trip point in the alarm
upper boundary register, and a lower trip point in the alarm lower boundary register. When
enabled, the event output will be triggered whenever entering or exiting (crossing above or
below) the alarm window.
4.4.2 Critical trip
The device can be programmed in such a way that the event output is only triggered when
the temperature exceeds the critical trip point. The critical temperature setting is
programmed in the critical temperature register. When the temperature sensor reaches the
critical temperature value in this register, the device is automatically placed in comparator
mode, which means that the critical event output cannot be cleared by using software to set
the clear event bit.
Table 15. Temperature trip point register format
Table 16. Alarm temperature upper boundary register format Bit 2 is LSB for default 10-bit mode. Depending on status of the resolution register, bit 1 may display 0.125 °C value. Depending on status of the resolution register, bit 0 may display 0.0625 °C value.
Table 17. Alarm temperature lower boundary register format Bit 2 is LSB for default 10-bit mode. Depending on status of the resolution register, bit 1 may display 0.125 °C value. Depending on status of the resolution register, bit 0 may display 0.0625 °C value.
