SN74LVC1G374DCKR ,Single D-Type Flip-Flop with 3-State Output SCES520C–DECEMBER 2003–REVISED DECEMBER 2013(1)Recommended Operating ConditionsMIN MAX UNITOperati ..
SN74LVC1G386DBVR ,SINGLE 3-INPUT POSITIVE-XOR GATE SCES439E–APRIL 2003–REVISED DECEMBER 2013(1)Recommended Operating ConditionsMIN MAX UNITOperating ..
SN74LVC1G386DCKR ,SINGLE 3-INPUT POSITIVE-XOR GATEmaximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
SN74LVC1G386DCKR ,SINGLE 3-INPUT POSITIVE-XOR GATEFEATURES DESCRIPTIONThe SN74LVC1G386 device performs the Boolean2• Available in the Texas Instrumen ..
SN74LVC1G38DBVR ,Single 2-Input NAND Gate with Open Drain OutputElectrical Characteristics....... 612 Device and Documentation Support........ 146.6 Switching Char ..
SN74LVC1G38DBVR ,Single 2-Input NAND Gate with Open Drain OutputFeatures 3 DescriptionThe SN74LVC1G38 device is designed for 1.65-V to1• Latch-Up Performance Excee ..
SP4916 , 2·5GHz /4512 PRESCALER
SP4916 , 2·5GHz /4512 PRESCALER
SP491ECP , Enhanced Full Duplex RS-485 Transceivers
SP491ECP , Enhanced Full Duplex RS-485 Transceivers
SP491EEP , Enhanced Full Duplex RS-485 Transceivers
SP491EEP , Enhanced Full Duplex RS-485 Transceivers
SN74LVC1G374DBVR-SN74LVC1G374DCKR
Single D-Type Flip-Flop with 3-State Output 6-SC70 -40 to 125
(TOP
DCK PACKAGE
(TOP VIEW) 4DGNDCLK
YEPOR YZP PACKAGE
(BOTTOM VIEW)GND VCC6CLK 4 Q the positive transitionof the clock (CLK) input, the
• Supports 5-V VCC Operation Q outputis setto the logic level setupat the data (D)
• Inputs Accept Voltagesto 5.5V input.
Provides Down Translationto VCC A buffered output-enable (OE) input can be usedto
• Max tpdof4nsat 3.3V place the outputin eithera normal logic state (highor
low logic levels)or the high-impedance state.In the
• Low Power Consumption, 10-μA Max ICChigh-impedance state, the output neither loads nor
• ±24-mA Output Driveat 3.3V drives the bus lines significantly. The high-impedance
• Ioff Supports Live Insertion, Partial-Power- state and increased drive provide the capabilityto
Down Mode, and Back Drive Protection drive bus lines without interface or pullup
components.
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, ClassII operationsof the flip-
ESD Protection Exceeds JESD22or new data can be arein the high-impedance
– 2000-V Human-Body Model (A114-A)– 200-V Machine Model (A115-A) state during power up
– 1000-V Charged-Device Model (C101) be tiedto VCC througha valueof the resistoris
DESCRIPTION capability of theThis single D-type latchis designed for 1.65-VV VCC operation. for partial-power-downThe SN74LVC1G374 features a 3-state Ioff circuitry disables thedesigned specifically for driving highly capacitive current backflowrelatively low-impedance loads. This device is through the device whenitis powered down.particularly suitable for implementing buffer registers,
input/output (I/O) ports, bidirectional bus drivers, and
working registers.
