SN65LVDS84AQDGGRQ1 ,Automotive Catalog FlatLink Transmitter 48-TSSOP -40 to 125FEATURESDGG PACKAGE2• 21:3 Data Channel Compression at up to(TOP VIEW)196 Mbytes/s ThroughputD4 D3• ..
SN65LVDS86AQDGGRG4 ,Automotive Catalog FlatLink Receiver 48-TSSOP -40 to 125FEATURESDGG PACKAGE2• 3:21 Data Channel Expansion at up to(TOP VIEW)178.5 Mbytes/s ThroughputD17 V• ..
SN65LVDS86AQDGGRQ1 ,Automotive Catalog FlatLink Receiver 48-TSSOP -40 to 125 SLLS768A–AUGUST 2006–REVISED JANUARY 2012ÇÇÉÉÇÇÇÉÉÇÇÇÇÉÉÇÇÇÉÉÇÇCLKINÇÇÉÉÇÇÇÉÉÇÇPrevious Cycle Curr ..
SN65LVDS93ADGGR ,10MHzFeatures 2 Applications1• Industrial Temperature Range –40°C to 85°C • LCD Display Panel Drivers• L ..
SN65LVDS93DGG ,Serdes (Serializer/Deserializer) TransmitterFEATURESeach loaded into registers upon the edge of the input• 28:4 Data Channel Compression at up ..
SN65LVDS93DGGR ,Serdes (Serializer/Deserializer) Transmitter........ SLLS302G–MAY 1998–REVISED MAY 2009ÉÉÉÉÉÉÉÉÉÉÉÉÉÉD0ÉÉÉÉÉÉÉÉÉÉÉÉÉÉCLKINorÉÉÇÇÇÉÉÇÇCLKINÉÉÇÇÇ ..
SN74HCT08D ,Quadruple 2-Input Positive-AND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HCT08DBLE ,Quadruple 2-Input Positive-AND GatesSN54HCT08, SN74HCT08QUADRUPLE 2-INPUT POSITIVE-AND GATESSCLS063D – NOVEMBER 1988 – REVISED AUIGUST ..
SN74HCT08DBR ,Quadruple 2-Input Positive-AND Gateslogic diagram (positive logic)AYB†absolute
SN74HCT08DR ,Quadruple 2-Input Positive-AND GatesSN54HCT08, SN74HCT08QUADRUPLE 2-INPUT POSITIVE-AND GATESSCLS063D – NOVEMBER 1988 – REVISED AUIGUST ..
SN74HCT08N ,Quadruple 2-Input Positive-AND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HCT08NSR ,Quadruple 2-Input Positive-AND Gatesmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN65LVDS84AQDGGRQ1
Automotive Catalog FlatLink Transmitter 48-TSSOP -40 to 125
1FEATURESVCC
GND
VCC
D10
GND
D11
D12
D13
D14
GND
D15
D16
D17
VCC
D18
D19
GND
GND
LVDSGND
Y0M
Y0P
Y1M
Y1P
LVDSVCC
LVDSGND
Y2M
Y2P
CLKOUTM
CLKOUTP
LVDSGND
PLLGND
PLLVCC
PLLGND
SHTDN
CLKIN
D20
DGG PACKAGE
(TOP VIEW)NC − Not Connected
DESCRIPTION/ORDERING INFORMATION
www.ti.com........................................................................................................................................................ SLLS766A–AUGUST 2006–REVISED APRIL 2008
FlatLink™ TRANSMITTER 21:3 Data Channel Compressionat upto
196 Mbytes/s Suited for SVGA, XGA,or SXGA Data
Transmission From Controllerto Display With
Very Low EMI 21 Data Channels Plus ClockIn Low-Voltage
TTL Inputs3 Data Channels Plus Clock
Out Low-Voltage Differential Signaling (LVDS)
Outputs Operates Froma Single 3.3-V Supply and mW (Typ) Packagedin Shrink Small-Outline
Package (TSSOP) With 20-Mil Terminal Pitch Consumes Than 0.54 mW When Disabled Wide Phase-Lock Input Frequency Range: MHzto75 No External Required for PLL Outputs Meetor Exceed the Requirementsof
ANSI EIA/TIA-644 Standard SSC Tracking Capabilityof 3% Center Spread 50-kHz Modulation Frequency Improved Replacement for SN75LVDS84 and
NSC DS90CF363A 3-V Device Qualified for ApplicationsThe SN65LVDS84AQ FlatLink™ transmitter contains three parallel-load serial-out shift registers, and four
low-voltage differential signaling (LVDS) line driversina single integrated circuit. These functions allow21 bitsof
single-ended LVTTL datato be synchronously transmitted over3 balanced-pair conductors for receipt bya
compatible receiver, suchas the SN75LVDS82or SN75LVDS86/86A.
When transmitting, data bits D0–D20 are each loaded into registersof the SN65LVDS84AQ upon the falling
edge. The internal PLLis frequency-lockedto CLKIN and usedto unload the data registersin 7-bit slices.
The three serial anda phase-locked clock (CLKOUT) are then outputto LVDS output drivers. The
frequencyof CLKOUTis the sameas the input clock, CLKIN.
The SN65LVDS84AQ requiresno external components andor no control. The data bus appears the same the inputto the and outputof the receiver with data transmission transparentto the user(s). The
only user interventionis the possible useof the shutdown/clear (SHTDN) active-low inputto inhibit the clock and
