SC16C650BIBS ,5 V, 3.3 V and 2.5 V UART with 32-byte FIFOs and infrared (IrDA) encoder/decoderfeatures are the 32-byte receiveand transmit FIFOs, automatic hardware or software flow control and ..
SC16C652B , 5V, 3.3 V and 2.5V dual UART, 5 Mbit/s (max.),with 32-byte FIFOs and infrared(IrDA) encoder/decoder
SC16C652BIB48 ,5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs and infrared (IrDA) encoder/decoderBlock diagramSC16C652BTRANSMIT TRANSMITFIFO SHIFT TXA, TXBREGISTER REGISTERD0 to D7DATA BUSIORANDIO ..
SC16C652BIB48 ,5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs and infrared (IrDA) encoder/decoderFeatures■ 2 channel UART■ 5 V, 3.3 V and 2.5 V operation■ 5 V tolerant inputs■ Industrial temperatu ..
SC16C652BIBS ,5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs and infrared (IrDA) encoder/decoderfeatures may betailored by software to meet specific user requirements. An internal loop-back capabi ..
SC16C652BIBS ,5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs and infrared (IrDA) encoder/decoderGeneral descriptionThe SC16C652B is a 2 channel Universal Asynchronous Receiver and Transmitter(UAR ..
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SDB0540 , Schottky Barrier Rectifier
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SDB10150PI , DUAL COMMON CATHODE SCHOTTKY RECTIFIER
SDB102 , 1 Amp Single Phase Glass Passivated Bridge Rectifier 50 to 1000 Volts
SDB103 , 1 Amp Single Phase Glass Passivated Bridge Rectifier 50 to 1000 Volts
SC16C650BIB48-SC16C650BIBS
5 V, 3.3 V and 2.5 V UART with 32-byte FIFOs and infrared (IrDA) encoder/decoder
General descriptionThe SC16C650Bisa Universal Asynchronous Receiver and Transmitter (UART) usedfor
serial data communications. Its principal function is to convert parallel data into serial
data, and vice versa. The UART can handle serial data rates up to 3 Mbit/s.
The SC16C650B is pin compatible with the ST16C650A and it will power-up to be
functionally equivalent to the 16C450. Programming of control registers enables the
added featuresof the SC16C650B. Someof these added features are the 32-byte receive
and transmit FIFOs, automatic hardware or software flow control and infrared
encoding/decoding. The selectable auto-flow control feature significantly reduces software
overload and increases system efficiency whilein FIFO modeby automatically controlling
serial data flow using RTS output and CTS input signals. The SC16C650B also provides
DMA mode data transfers through FIFO trigger levels and the RXRDY and TXRDY
signals. On-board status registers provide the user with error indications, operational
status, and modem interface control. System interrupts may be tailored to meet user
requirements. An internal loopback capability allows on-board diagnostics.
The SC16C650B operates at 5V , 3.3 V and 2.5 V, and the industrial temperature range,
and is available in plastic PLCC44, LQFP48, and HVQFN32 packages.
Features Single channel5V , 3.3 V and 2.5 V operation5 V tolerant on input only pins1 Industrial temperature range (−40 °C to +85 °C) After reset, all registers are identical to the typical 16C450 register set Capable of running with all existing generic 16C450 software Pin compatibility with the industry-standard ST16C450/550, TL16C450/550,
PC16C450/550. Software compatible with ST16C650. Upto3 Mbit/s transmit/receive operationat5V,2 Mbit/sat 3.3V, and1 Mbit/sat 2.5V 32 byte transmit FIFO 32 byte receive FIFO with error flags Programmable auto-RTS and auto-CTS In auto-CTS mode, CTS controls transmitter In auto-RTS mode, RX FIFO contents and threshold control RTS Automatic software/hardware flow control
SC16C650B
5 V, 3.3 V and 2.5 V UART with 32-byte FIFOs and infrared
(IrDA) encoder/decoder
Rev. 04 — 14 September 2009 Product data sheet For data bus pins D7 to D0, see Table 26 “Limiting values”.
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder Programmable Xon/Xoff characters Software selectable baud rate generator Supports IrDA version 1.0 (up to 115.2 kbit/s) Four selectable Receive and T ransmit FIFO interrupt trigger levels Standard modem interface or infrared IrDA encoder/decoder interface Sleep mode Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break) Independent receiver clock input Transmit, Receive, Line Status, and Data Set interrupts independently controlled Fully programmable character formatting: 5, 6, 7, or 8-bit characters Even, odd, or no-parity formats 1, 11 ⁄2, or 2-stop bit Baud generation (DC to 3 Mbit/s) False start-bit detection Complete status reporting capabilities 3-state output TTL drive capabilities for bidirectional data bus and control bus Line break generation and detection Internal diagnostic capabilities: Loopback controls for communications link fault isolation Prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR, RI, DCD)
Ordering information
Table 1. Ordering informationIndustrial: VCC= 2.5 V, 3.3 V or 5V±10 %; Tamb= −40 °C to +85 °C.
SC16C650BIA44 PLCC44 plastic leaded chip carrier; 44 leads SOT187-2
SC16C650BIB48 LQFP48 plastic low profile quad flat package; 48 leads; body7×7× 1.4 mm SOT313-2
SC16C650BIBS HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; terminals; body5×5× 0.85 mm
SOT617-1
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder Block diagram
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder Pinning information
5.1 Pinning
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
5.2 Pin description
Table 2. Pin description 31 28 18 I
Register select.A0to A2 are sued during read and write
operations to select the UART register to read from or write to.
Refer to Table 3 for register addresses and refer to signal AS
description. 30 27 17 I 29 26 16 I 28 24 - I
Address strobe. When AS is active (LOW), A0, A1 and A2 and
CS0 CS1 and CS2 drive the internal select logic directly. WhenAS
is HIGH, the register select and chip select signals are held at the
logic levels they were in when the LOW-to-HIGH transition of AS
occurred.
BAUDOUT 17 12 8 O
Baud out. BAUDOUT is a 16× clock signal for the transmitter
section of the UART. The clock rate is established by the reference
oscillator frequency divided by a divisor specified in the baud
generator divisor latches. BAUDOUT may also be used for the
receiver section by tying this output to RCLK.
CS0 14 9 - I
Chip select. When CS0 and CS1 are HIGH and CS2is LOW, these inputs selectthe UART. When anyof these inputs are inactive, the
UART remains inactive (refer to AS description).CS1 15 10 - I
CS2 16 11 - I - - 7 I
CTS 40 38 25 I
Clear to send. CTS is a modem status signal. Its condition can be
checked by reading bit 4 (CTS) of the Modem Status Register
(MSR). MSR[0] (ΔCTS) indicates that CTS has changed states
since the last read from the MSR. If the modem status interrupt is
enabled when CTS changes levels and the auto-CTS mode is not
enabled, an interrupt is generated. CTS is also used in the
auto-CTS mode to control the transmitter.
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder 2 43 28 I/O
Data bus. Eight data lines with 3-state outputs provide a
bidirectional path for data, control and status information between
the UART and the CPU.D1 3 44 29 I/O 4 45 30 I/O 5 46 31 I/O 6 47 32 I/O 7 2 1 I/O 8 3 2 I/O 9 4 3 I/O
DCD 42 40 - I
Data carrier detect. DCD is a modem status signal. Its condition
can be checked by reading MSR[7] (DCD). MSR[3] (ΔDCD)
indicates that DCD has changed states since the last read from the
MSR.If the modem status interruptis enabled when DCD changes
levels, an interrupt is generated.
DDIS 26 22 - O
Driver disable. DDIS is active (LOW) when the CPU is reading
data. When inactive (HIGH), DDIS can disable an external
transceiver.
DSR 41 39 26 I
Data set ready. DSRisa modem status signal.Its condition canbe
checked by reading MSR[5] (DSR). MSR[1] (ΔDSR) indicates DSR
has changed levels since the last read from the MSR.If the modem
status interruptis enabled when DSR changes levels,an interruptis
generated.
DTR 37 33 22 O
Data terminal ready. When active (LOW), DTR informs a modem dataset thatthe UARTis readyto establish communication. DTR
is placed in the active level by setting the DTR bit of the Modem
Control Register. DTR is placed in the inactive level either as a
result of a Master Reset, during loopback mode operation, or
clearing the DTR bit.
INT 33 30 20 O
Interrupt. When active (HIGH), INT informs the CPU thatthe UART
has an interrupt to be serviced. Four conditions that cause an
interrupt to be issued are: a receiver error, received data that is
available or timed out (FIFO mode only), an empty transmitter
holding register or an enabled modem status interrupt. INT is reset
(deactivated) either when the interruptis servicedorasa resultofa
Master Reset.
OUT1 38 34 - O
Outputs 1 and 2. These are user-designated output terminals thataresetto the active (low) levelby setting respective Modem Control
Register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2 are setto
the inactive (HIGH) level as a result of Master Reset, during
loopback mode operations, or by clearing bit 2 (OUT1) or bit3
(OUT2) of the MCR.
OUT2 35 31 - O
OUT - - 23 O
RCLK 10 5 4 I
Receiver clock. RCLK is the 16× baud rate clock for the receiversection of the UART.
IOR 25 20 - I
Read inputs. When either IOR or IOR is active (LOW or HIGH,
respectively) while the UART is selected, the CPU is allowed to
read status informationor data froma selected UART register. Only
oneof these inputsis requiredfor the transferof data duringa read
operation; the other input should be tied to its inactive level (i.e.,
IOR tied LOW or IOR tied HIGH).
IOR 24 19 14 I
Table 2. Pin description …continued
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoderRESET 39 35 24 I
Master Reset. When active (HIGH), MR clears most UARTregisters and sets the levels of various output signals. 43 41 - I
Ring indicator. RI is a modem status signal. Its condition can be
checkedby reading MSR[6] (RI). MSR[2] (ΔRI) indicates thatRI has
changed from a LOW to a HIGH level since the last read from the
MSR. If the modem status interrupt is enabled when this transition
occurs, an interrupt is generated.
RTS 36 32 21 O
Request to send. When active, RTS informs the modem or data
set that the UART is ready to receive data. RTS is set to the active
levelby settingthe RTS modem control registerbit andissetto the
inactive (HIGH) level either as a result of a Master Reset or during
loopback mode operationsorby clearingbit1 (RTS)of the MCR.In
the auto-RTS mode, RTS is set to the inactive level by the receiver
threshold control logic.
RXRDY32 29 19 O
Receiver ready. Receiver direct memory access (DMA) signalingis
available with RXRDY. When operating in the FIFO mode, one of
two typesof DMA signaling canbe selected using the FIFO Control
Register bit 3 (FCR[3]). When operating in the 16C450 mode, only
DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in
which a transfer is made between CPU bus cycles. Mode1
supports multi-transfer DMA in which multiple transfers are made
continuously until the receiver FIFO has been emptied. In DMA
mode 0 (FCR[0]= 0 or FCR[0]= 1, FCR[3]= 0), when there is at
least one character in the receiver FIFO or Receive Holding
Register, RXRDY is active (LOW). When RXRDY has been active
but there are no characters in the FIFO or holding register, RXRDY
goes inactive (HIGH). In DMA mode 1 (FCR[0]= 1, FCR[3]=1),
when the trigger level or the time-out has been reached, RXRDY
goes active (LOW); when it has been active but there are no more
characters in the FIFO or holding register, it goes inactive (HIGH). 11 7 5 I
Serial data input. RX is serial data input from a connectedcommunications device. 13 8 6 O
Serial data output. TX is composite serial data output to aconnected communication device. TX is set to the marking (HIGH)
level as a result of Master Reset.
TXRDY27 23 15 O
Transmitter ready. Transmitter DMA signaling is available withTXRDY. When operating in the FIFO mode, one of two types of
DMA signaling can be selected using FCR[3]. When operating in
the 16C450 mode, only DMA mode 0 is allowed. Mode 0 supports
single-transfer DMA in which a transfer is made between CPU bus
cycles. Mode 1 supports multi-transfer DMA in which multiple
transfers are made continuously until the transmit FIFO has been
filled.
VCC 44 42 27 power
2.5 V, 3 V or 5 V supply voltage.GND 22 18 13[1] power
Ground voltage.IOW 21 17 - I
Write inputs. When either IOW or IOW is active (LOW or HIGH,
respectively) and while the UARTis selected, the CPUis allowedto
write control wordsor data intoa selected UART register. Only one
of these inputs is required to transfer data during a write operation;
the other input shouldbe tiedtoits inactive level (i.e., IOW tied LOW IOW tied HIGH).
IOW20 16 11 I
Table 2. Pin description …continued
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder[1] HVQFN32 package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
[2] In Sleep mode, XTAL2 is left floating.
Functional descriptionThe SC16C650B provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessaryfor converting the serial data stream into
parallel data that is required with digital data systems. Synchronization for the serial data
stream is accomplished by adding start and stop bits to the transmit data to form a data
character (character orientated protocol). Data integrityis insuredby attachinga paritybit
to the data character. The parity bit is checked by the receiver for any transmission bit
errors. The SC16C650B is fabricated with an advanced CMOS process to achieve low
drain power and high speed requirements.
The SC16C650B is an upward solution that provides 32 bytes of transmit and receive
FIFO memory, instead of none in the 16C450, or 16 bytes in the 16C550. The
SC16C650B is designed to work with high speed modems and shared network
environments that require fast data processing time. Increased performanceis realizedin
the SC16C650B by the larger transmit and receive FIFOs. This allows the external
processor to handle more networking tasks within a given time. In addition, the four
selectable levelsof FIFO trigger interrupt and automatic hardware/software flow controlis
uniquely provided for maximum data throughput performance, especially when operating
in a multi-channel environment. The combination of the above greatly reduces the
bandwidth requirement of the external controlling CPU, increases performance, and
reduces power consumption.
The SC16C650Bis capableof operationupto3 Mbit/s witha48 MHz external clock input
(at 5 V).
The rich feature set of the SC16C650B is available through internal registers. Automatic
hardware/software flow control, selectable transmit and receive FIFO trigger level,
selectable TX and RX baud rates, modem interface controls, anda Sleep mode are some
of these features.
XTAL1 18 14 9 I
Crystal connection or external clock input.XTAL2[2] 19 15 10 O
Crystal connection or the inversion of XTAL1 if XTAL1 is
driven.n.c. 1,12,23,
1, 6, 13,
21, 25,
36, 37, - not connected
Table 2. Pin description …continued
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
6.1 Internal registersThe SC16C650B provides17 internal registersfor monitoring and control. These registers
are shown in Table 3. T welve registers are similar to those already available in the
standard 16C550. These registers functionas data holding registers (THR/RHR), interrupt
status and control registers (IER/ISR), a FIFO control register (FCR), line status and
control registers (LCR/LSR), modem status and control registers (MCR/MSR),
programmable data rate (clock) control registers (DLL/DLM), and a user accessible
ScratchPad Register (SPR). Beyond the general 16C550 features and capabilities, the
SC16C650B offers an enhanced feature register set (EFR, Xon1/Xoff1, Xon2/Xoff2) that
provides on-board hardware/software flow control. Register functions are more fully
described in the following paragraphs.
[1] These registers are accessible only when LCR[7] is a logic0.
[2] These registers are accessible only when LCR[7] is a logic1.
[3] Enhanced Feature Register, Xon1, Xon2 and Xoff1, Xoff2 are accessible only when the LCR is set to BFh.
6.2 FIFO operationThe 32-byte transmit and receive data FIFOs are enabled by the FIFO Control Register
bit0 (FCR[0]). With 16C550 devices, the user can set the receive trigger level, but not the
transmit trigger level. The SC16C650B provides independent trigger levels for both
receiver and transmitter. To remain compatible with SC16C550, the transmit interrupt
trigger level is set to 16 following a reset. It should be noted that the user can set the
transmit trigger levelsby writingto the FCR register, but activation will not take place until
EFR[4]is settoa logic1. The receiver FIFO section includesa time-out functionto ensure
Table 3. Internal registers decoding
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR)[1] 0 0 Receive Holding Register Transmit Holding Register 0 1 Interrupt Enable Register Interrupt Enable Register 1 0 Interrupt Status Register FIFO Control Register 1 1 Line Control Register Line Control Register 0 0 Modem Control Register Modem Control Register 0 1 Line Status Register n/a 1 0 Modem Status Register n/a 1 1 Scratchpad Register Scratchpad Register
Baud rate register set (DLL/DLM)[2] 0 0 LSB of Divisor Latch LSB of Divisor Latch 0 1 MSB of Divisor Latch MSB of Divisor Latch
Enhanced register set (EFR, Xon1, Xoff1, Xon2, Xoff2)[3] 1 0 Enhanced Feature Register Enhanced Feature Register 0 0 Xon1 word Xon1 word 0 1 Xon2 word Xon2 word 1 0 Xoff1 word Xoff1 word 1 1 Xoff2 word Xoff2 word
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoderdata is delivered to the external CPU. An interrupt is generated whenever the Receive
Holding Register (RHR) has not been read following the loading of a character or the
receive trigger level has not been reached.
6.3 Hardware flow controlWhen automatic hardware flow controlis enabled, the SC16C650B monitors the CTS pin
for a remote buffer overflow indication and controls the RTS pin for local buffer overflows.
Automatic hardware flow controlis selectedby setting EFR[6] (RTS) and EFR[7] (CTS)to
a logic 1. If CTS changes from a logic 0 to a logic 1 indicating a flow control request,
ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the SC16C650B will suspend
TX transmissions as soon as the stop bit of the character in process is shifted out.
Transmissionis resumed after the CTS input returnstoa logic0, indicating more data may
be sent.
With the auto-RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1 (RTS
off), until the receive FIFO reaches the next trigger level. However, the RTS pin will return
to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below the
programmed trigger level. However, under the above described conditions, the
SC16C650B will continue to accept data until the receive FIFO is full.
6.4 Software flow controlWhen software flow control is enabled, the SC16C650B compares one or two sequential
receive data characters with the programmed Xon or Xoff character value(s). If received
character(s) match the programmed Xoff values, the SC16C650B will halt transmission
(TX) as soon as the current character(s) has completed transmission. When a match
occurs, the receive ready (if enabled via Xoff IER[5]) flags will be set and the interrupt
output pin(if receive interruptis enabled) willbe activated. Followinga suspension dueto
a match of the Xoff characters’ values, the SC16C650B will monitor the receive data
stream for a match to the Xon1, Xon2 character value(s). If a match is found, the
SC16C650B will resume operation and clear the flags (ISR[4]).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic0.
Following reset, the user can write any Xon/Xoff value desired for software flow control.
Different conditions can be set to detect Xon/Xoff characters and suspend/resume
transmissions. When double 8-bit Xon/Xoff characters are selected, the SC16C650B
compares two consecutive receive characters with two software flow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above
described flow control mechanisms, flow control characters are not placed (stacked)in the
user accessible RX data buffer or FIFO. When using a software flow control the Xon/Xoff
characters cannot be used for data transfer.
Table 4. Flow control mechanism 8 0 16 16 7 24 24 15 28 28 23
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder the event that the receive bufferis overfilling and flow control needstobe executed, the
SC16C650B automatically sends an Xoff message (when enabled) via the serial TX
outputto the remote modem. The SC16C650B sends the Xoff1/Xoff2 charactersas soon
as received data passes the programmed trigger level. To clear this condition, the
SC16C650B will transmit the programmed Xon1/Xon2 charactersas soonas receive data
drops below the next low or programmed trigger level.
6.5 Special feature software flow controlA special feature is provided to detect an 8-bit character when EFR[5] is set. When 8-bit
characteris detected,it willbe placedon the user-accessible data stack along with normal
incoming RX data. This condition is selected in conjunction with EFR[3:0]. Note that
software flow control should be turned off when using this special mode by setting
EFR[3:0] to a logic0.
The SC16C650B compares each incoming receive character with Xoff2 data. If a match
exists, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate
detection of a special character. Although Table 8 “SC16C650B internal registers” shows
each X-register with eight bits of character information, the actual number of bits is
dependenton the programmed word length. Line Control Register bits LCR[1:0] define the
numberof character bits, i.e., either5 bits,6 bits,7 bitsor8 bits. The word length selected
by LCR[1:0] also determine the number of bits that will be used for the special character
comparison.Bit0in the X-registers corresponds with the LSBbitfor the receive character.
6.6 Hardware/software and time-out interruptsThree special interrupts have been added to monitor the hardware and software flow
control. The interrupts are enabled by IER[7:5]. Care must be taken when handling these
interrupts. Following a reset, the transmitter interrupt is enabled, the SC16C650B will
issue an interrupt to indicate that the Transmit Holding Register is empty. This interrupt
must be serviced prior to continuing operations. The ISR register provides the current
singular highest priority interrupt only.It couldbe noted that CTS and RTS interrupts have
lowest interrupt priority. A condition can exist where a higher priority interrupt may mask
the lower priority CTS/RTS interrupt(s). Only after servicing the higher pending interrupt
will the lower priority CTS/RTS interrupt(s)be reflectedin the status register. Servicing the
interrupt without investigating further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time-Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the SC16C650B
FIFO may hold more characters than the programmed trigger level. Following the removal
of a data byte, the user should re-check LSR[0] for additional characters. A Receive
Time-Out will not occur if the receive FIFO is empty. The time-out counter is reset at the
centerof each stopbit receivedor each time the Receive Holding Register (RHR)is read.
The actual time-out value is 4 character time.
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
6.7 Programmable baud rate generatorThe SC16C650B supports high speed modem technologies that have increased input
data rates by employing data compression schemes. For example, a 33.6 kbit/s modem
that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s
ISDN modem that supports data compression may needan input data rateof 460.8 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable baud rate generatoris capableof
accepting an input clock up to 48 MHz, as required for supporting a 3 Mbit/s data rate.
The SC16C650B can be configured for internal or external clock operation. For internal
clock oscillator operation, an industry standard microprocessor crystal (parallel resonant, pF to 33 pF load) is connected externally between the XTAL1 and XTAL2 pins (see
Figure 5). Alternatively, an external clock can be connected to the XTAL1 pin to clock the
internal baud rate generator for standard or custom rates (seeT able 5).
The generator divides the input 16× clock by any divisor from 1 to (216− 1). The
SC16C650B divides the basic crystal or external clock by 16. The frequency of the
BAUDOUT output pin is exactly 16× (16 times) the selected baud rate
(BAUDOUT=16× baud rate). Customized baud rates can be achieved by selecting the
proper divisor values for the MSB and LSB sections of baud rate generator.
Setting MCR[7]toa logic1 providesan additional divide-by-4, whereas setting MCR[7]to
a logic 0 only divides by 1 (seeT able 5 and Figure6).
Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a
user capability for selecting the desired final baud rate. The example inT able 5 shows
selectable baud rates when using a 1.8432 MHz crystal and setting MCR[7] to a logic0.
For custom baud rates, the divisor value can be calculated using Equation1:
(1)
divisor in decimal() XTAL1 clock frequency
serial data rate 16× ----------------------------------------------------------------=
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
Table 5. Baud rates using 1.8432 MHz or 3.072 MHz crystal
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
6.8 DMA operationThe SC16C650B FIFO trigger level provides additional flexibility to the user for block
mode operation. The user can optionally operate the transmit and receive FIFOs in the
DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY output
pins.T able 6 andT able 7 show this.
Remark: DMA operation is not supported in the HVQFN32 package.
6.9 Sleep modeThe SC16C650B is designed to operate with low power consumption. A special Sleep
mode is included to further reduce power consumption when the chip is not being used.
With EFR[4] and IER[4] enabled (set to a logic 1), the SC16C650B enters the Sleep
mode, but resumes normal operation when a start bit is detected, a change of state on
any of the modem input pins RI, CTS, DSR, DCD, RX pin, or a transmit data is provided the user.If the Sleep modeis enabled and the SC16C650Bis awakenedby oneof the
conditions described above, it will return to the Sleep mode automatically after the last
character is transmitted or read by the user. In any case, the Sleep mode will not be
entered while an interrupt(s) is pending. The SC16C650B will stay in the Sleep mode of
operation until it is disabled by setting IER[4] to a logic0.
6.10 Loopback modeThe internal loopback capability allows on-board diagnostics. In the loopback mode, the
normal modem interface pins are disconnected and reconfigured for loopback internally.
MCR[3:0] register bits are usedfor controlling loopback diagnostic testing.In the loopback
mode, OUT1 (bit2) and OUT2 (bit3)in the MCR register control the modemRI and DCD
inputs, respectively. MCR signals DTR (bit 0) and RTS (bit 1) are used to control the
modem DSR and CTS inputs, respectively. The transmitter output (TX) and the receiver
input (RX) are disconnected from their associated interface pins, and instead are
connected together internally (see Figure 7). The CTS, DSR, DCD, and RI are
disconnected from their normal modem control input pins, and instead are connected
internallyto DTR, RTS, OUT1 and OUT2. Loopback test datais entered into the Transmit
Holding Register via the user data bus interface, D0to D7. The transmit UART serializes
the data and passes the serial data to the receive UART via the internal loopback
connection. The receive UART converts the serial data back into parallel data thatis then
made available at the user data interface D0to D7. The user optionally compares the
received data to the initial transmitted data for verifying error-free operation of the UART
TX/RX circuits.
Table 6. Effect of DMA mode on state of RXRDY pin1 = FIFO empty 0-to-1 transition when FIFO empties
0 = at least 1 byte in FIFO 1-to-0 transition when FIFO reaches trigger level,or time-out occurs
Table 7. Effect of DMA mode on state of TXRDY pin1 = at least 1 byte in FIFO 0-to-1 transition when FIFO becomes full
0 = FIFO empty 1-to-0 transition when FIFO has 1 empty space
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoderIn this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational. However, the interrupts can only be read using
lower four bitsof the Modem Status Register (MSR[3:0]) insteadof the four Modem Status
Register bits 7:4. The interrupts are still controlled by the IER.
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder Register descriptionsTable8 details the assignedbit functionsfor the seventeen SC16C650B internal registers.
The assigned bit functions are more fully defined in Section 7.1 through Section 7.11.
[1] The value shown represents the register’s initialized HEX value; X= n/a.
[2] These registers are accessible only when LCR[7]=0.
[3] These bits are only accessible when EFR[4] is set.
[4] This function is not supported in the HVQFN32 package, and should not be written.
[5] OUT2 pin is not supported in the HVQFN32 package, and this bit should not be written.
Table 8. SC16C650B internal registers
General register set[2]
Special register set[7]
Enhanced register set[8]
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder[6] This bit controls the OUT pin in the HVQFN32 package, and OUT1 in the other packages.
[7] The Special register set is accessible only when LCR[7] is set to a logic 1.
[8] Enhanced Feature Register (EFR), Xon1, Xon2 Xoff1, Xoff2 are accessible only when LCR is set to BFh.
7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR)The serial transmitter section consists of an 8-bit Transmit Holding Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D[7:0]) to the
THR, providing that the THRor TSRis empty. The THR empty flagin the LSR register will
be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR.
Note that a write operation can be performed when the THR empty flag is set
(logic0= FIFO full; logic1= at least one FIFO location available).
The serial receive section also contains an 8-bit Receive Holding Register (RHR).
Receive data is removed from the SC16C650B and receive FIFO by reading the RHR
register. The receive section provides a mechanism to prevent false starts. On the falling
edge of a start or false start bit, an internal receiver counter starts counting clocks at the
16× clock rate. After 71 ⁄2 clocks, the start bit time should be shifted to the center of the
start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated.
Evaluating the start bit in this manner prevents the receiver from assembling a false
character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INT output pin.
Table 9. Interrupt Enable Register bits description IER[7] CTS interrupt.
logic 0 = disable the CTS interrupt (normal default condition)
logic1= enable the CTS interrupt. The SC16C650B issuesan interrupt when
the CTS pin transitions from a logic 0 to a logic 1. IER[6] RTS interrupt.
logic 0 = disable the RTS interrupt (normal default condition)
logic1= enable the RTS interrupt. The SC16C650B issuesan interrupt when
the RTS pin transitions from a logic 0 to a logic1. IER[5] Xoff interrupt.
logic 0 = disable the software flow control, receive Xoff interrupt (normal
default condition).
logic 1 = enable the software flow control, receive Xoff interrupt. See Section
6.4 “Software flow control” for details. IER[4] Sleep mode.
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode. See Section 6.9 “Sleep mode” for details. IER[3] Modem Status Interrupt.
logic 0 = disable the modem status register interrupt (normal default
condition)
logic 1 = enable the modem status register interrupt
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
7.2.1 IER versus receive FIFO interrupt mode operationWhen the receive FIFO (FCR[0]= logic 1), and receive interrupts (IER[0]= logic 1) are
enabled, the receive interrupts and register status will reflect the following:
The receive data available interrupts are issued to the external CPU when the FIFO
has reached the programmed trigger level. It will be cleared when the FIFO drops
below the programmed trigger level.
FIFO status will also be reflected in the user accessible ISR register when the FIFO
trigger level is reached. Both the ISR register status bit and the interrupt will be
cleared when the FIFO drops below the trigger level.
The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift
register to the receive FIFO. It is reset when the FIFO is empty.
7.2.2 IER versus receive/transmit FIFO polled mode operationWhen FCR[0]= logic 1, resetting IER[3:0] enables the SC16C650B in the FIFO polled
mode of operation. Since the receiver and transmitter have separate bits in the LSR,
either or both can be used in the polled mode by selecting respective transmit or receive
control bit(s).
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[4:1] will provide the type of errors encountered, if any.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.
LSR[7] will indicate any FIFO data errors. IER[2] Receive Line Status interrupt. This interrupt will be issued whenever a fully
assembled receive character is transferred from RSR to the RHR/FIFO, i.e.,
data ready, LSR[0].
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt IER[1] Transmit Holding Register interrupt. This interrupt will be issued whenever the
THR is empty, and is associated with LSR[1].
logic 0 = disable the transmitter empty interrupt (normal default condition)
logic 1 = enable the transmitter empty interrupt IER[0] Receive Holding Register interrupt. This interrupt will be issued when the FIFO
has reached the programmed trigger level, or is cleared when the FIFO drops
below the trigger level in the FIFO mode of operation.
logic 0 = disable the receiver ready interrupt (normal default condition)
logic 1 = enable the receiver ready interrupt
Table 9. Interrupt Enable Register bits description …continued
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
7.3 FIFO Control Register (FCR)This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels, and select the DMA mode.
7.3.1 DMA mode
7.3.1.1 Mode 0 (FCR bit 3 = 0)Set and enable the interruptfor each single transmitor receive operation, andis similarto
the 16C450 mode. T ransmit Ready (TXRDY) will go to a logic 0 whenever an empty
transmit space is available in the Transmit Holding Register (THR). Receive Ready
(RXRDY) willgotoa logic0 whenever the Receive Holding Register (RHR)is loaded with
a character.
7.3.1.2 Mode 1 (FCR bit 3 = 1)Set and enable the interruptina block mode operation. The transmit interruptis set when
the transmit FIFOis below the programmed trigger level. The receive interruptis set when
the receive FIFO fills to the programmed trigger level. However, the FIFO continues to fill
regardlessof the programmed level until the FIFOis full. RXRDY remainsa logic0as long
as the FIFO fill level is above the programmed trigger level.
7.3.2 FIFO mode
Table 10. FIFO Control Register bits description7:6 FCR[7] (MSB),
FCR[6] (LSB)
RCVR trigger. These bits are usedtoset the trigger levelfor the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However,the FIFO will continueto
be loaded until it is full. Refer to Table 11.
5:4 FCR[5] (MSB),
FCR[4] (LSB)
Logic 0 or cleared is the default condition; TX trigger level= 16.
These bits are used to set the trigger level for the transmit FIFO
interrupt. The SC16C650B will issue a transmit empty interrupt when
the numberof charactersin FIFO drops belowthe selected trigger level.
Refer to Table 12. FCR[3] DMA mode select.
logic 0 = set DMA mode ‘0’ (normal default condition)
logic 1 = set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C650B is in the16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode
(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there
are no characters in the transmit FIFO or transmit holding register, the
TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a
logic 1 after the first character is loaded into the transmit holding
register.
Receive operation in mode ‘0’: When the SC16C650B is in 16C450mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and
there is at least one character in the receive FIFO, the RXRDY pin willa logic0. Once active,the RXRDYpin willgotoa logic1 when there
are no more characters in the receiver.
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder(cont.)
Transmit operation in mode ‘1’: When the SC16C650B is in FIFOmode (FCR[0] = logic 1; FCR[3]= logic 1), the TXRDY pin will be a
logic 1 when the transmit FIFO is completely full. It will be a logic0
when FIFO has 1 empty space.
Receive operation in mode ‘1’: When the SC16C650B is in FIFOmode (FCR[0]= logic1; FCR[3]= logic1) and the trigger level has been
reached,ora Receive Time-Out has occurred, the RXRDY pinwillgoto
a logic 0. Once activated, it will go to a logic 1 after there are no more
characters in the FIFO. FCR[2] XMIT FIFO reset.
logic 0 = no FIFO transmit reset (normal default condition)
logic1= clears the contentsofthe transmit FIFO and resets the FIFO
counter logic (the transmit shift registerisnot clearedor altered). This
bit will return to a logic 0 after clearing the FIFO. FCR[1] RCVR FIFO reset.
logic 0 = no FIFO receive reset (normal default condition)
logic1= clears the contentsof the receive FIFO and resets the FIFO
counter logic (the receive shift registeris not clearedor altered). This
bit will return to a logic 0 after clearing the FIFO. FCR[0] FIFO enable.
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic 1 = enable the transmit and receive FIFO.
This bit must be a
logic 1 when other FCR bits are written to, or they will not be
programmed.
Table 11. RCVR trigger levelsTable 12. TX FIFO trigger levels
Table 10. FIFO Control Register bits description …continued
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
7.4 Interrupt Status Register (ISR)The SC16C650B provides six levelsof prioritized interruptsto minimize external software
interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status
bits. Performing a read cycle on the ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are acknowledged until the pending
interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is
cleared. However, it should be noted that only the current pending interrupt is cleared by
the read. A lower level interrupt may be seen after re-reading the interrupt status bits.
Table 13 “Interrupt source” shows the data values (bits 0:5) for the six prioritized interrupt
levels and the interrupt sources associated with each of these interrupt levels.
Table 13. Interrupt source 0 0 0 1 1 0 LSR (receiver Line Status
Register) 0 0 0 1 0 0 RXRDY (Received Data Ready) 0 0 1 1 0 0 RXRDY (Receive Data time-out) 0 0 0 0 1 0 TXRDY (Transmitter Holding
Register Empty) 0 0 0 0 0 0 MSR (Modem Status Register) 0 1 0 0 0 0 RXRDY (Received Xoff signal) /
Special character 1 0 0 0 0 0 CTS, RTS change of state
Table 14. Interrupt Status Register bits description7:6 ISR[7:6] FIFOs enabled. These bits are set to a logic 0 when the FIFO is not being
used. They are set to a logic 1 when the FIFOs are enabled.
logic 0 or cleared = default condition
5:4 ISR[5:4] INT priority bits 4:3. These bits are enabled when EFR[4]is settoa logic1.
ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5]
indicates that CTS, RTS have been generated. Note that once set to a
logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received.
logic 0 or cleared = default condition
3:1 ISR[3:1] INT priority bits 2:0. These bits indicate the sourcefora pending interruptat
interrupt priority levels 1, 2, and 3 (see Table 13).
logic 0 or cleared = default condition ISR[0] INT status.
logic 0 = an interrupt is pending and the ISR contents may be used as a
pointer to the appropriate interrupt service routine.
logic 1 = no interrupt pending (normal default condition)
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
7.5 Line Control Register (LCR)The Line Control Register is used to specify the asynchronous data communication
format. The word length, the numberof stop bits, and the parity are selectedby writing the
appropriate bits in this register.
Table 15. Line Control Register bits description LCR[7] Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch and enhanced feature register enabled LCR[6] Set break. When enabled, the Break control bit causes a break condition to transmitted (theTX outputis forcedtoa logic0 state). This condition exists
until disabled by setting LCR[6] to a logic0.
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition LCR[5] Set parity. If the parity bit is enabled, LCR[5] selects the forced parity format.
Programs the parity conditions (see Table 16).
logic 0 = parity is not forced (normal default condition)
LCR[5]= logic1 and LCR[4]= logic0: paritybitis forcedtoa logic1for the
transmit and receive data
LCR[5]= logic1 and LCR[4]= logic1: paritybitis forcedtoa logic0for the
transmit and receive data LCR[4] Even parity. If the parity bit is enabled with LCR[3] set to a logic 1, LCR[4]
selects the even or odd parity format.
logic0= odd parityis generatedby forcingan odd numberof logic1sinthe
transmitted data. The receiver must be programmed to check the same
format (normal default condition).
logic 1 = even parity is generated by forcing an even number of logic 1s in
the transmitted data. The receiver mustbe programmedto check the same
format. LCR[3] Parity enable. Parity or no parity can be selected via this bit.
logic 0 = no parity (normal default condition)
logic 1 = a parity bit is generated during the transmission, receiver checks
the data and parity for transmission errors LCR[2] Stop bits. The length of stop bit is specified by this bit in conjunction with the
programmed word length (see Table 17).
logic 0 or cleared = default condition
1:0 LCR[1:0] Word length bits1,0. These two bits specify the word lengthtobe transmitted
or received (see Table 18).
logic 0 or cleared = default condition
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
7.6 Modem Control Register (MCR)This register controls the interface with the modem or a peripheral device.
Table 16. LCR[5] parity selection X 0 no parity 0 1 odd parity 1 1 even parity 0 1 force parity ‘1’ 1 1 forced parity ‘0’
Table 17. LCR[2] stop bit length 5, 6, 7, 8 1 1-1⁄2 6, 7, 8 2
Table 18. LCR[1:0] word lengthTable 19. Modem Control Register bits description MCR[7] Clock select.
logic 0 = divide-by-1. The input clock (crystal or external) is divided by 16 and
then presented to the programmable Baud Rate Generator (BGR) without
further modification, i.e., divide-by-1 (normal default condition).
logic 1 = divide-by-4. The divide-by-1 clock described in MCR[7] equals a
logic 0, is further divided by four (see also Section 6.7 “Programmable baud
rate generator”). MCR[6] IR enable.
logic 0 = enable the standard modem receive and transmit input/output
interface (normal default condition)
logic1= enable infrared IrDA receive and transmit inputs/outputs. Whilein this
mode, the TX/RX output/inputs are routed to the infrared encoder/decoder.
The data input and output levels will conform to the IrDA infrared interface
requirement. As such, while in this mode, the infrared TX output will be a
logic 0 during idle data conditions.
NXP Semiconductors SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder MCR[5] INT type select.
logic0= enable interrupt output mode (normal default condition)
logic1= enable open source interrupt output mode. Provides shared
interrupts by producing a wire-OR output driver capability for interrupts. This
output appears at the INT pin. When using this option, an external pull-down
resistor of 200Ωto 500 Ω must be tied from the INT pin to ground to provide
an acceptable logic 0 level MCR[4] Loopback. Enable the local loopback mode (diagnostics). In this mode the
transmitter output (TX) and the receiver input (RX), CTS, DSR, DCD, andRI are
disconnected from the SC16C650B I/O pins. Internally the modem data and
control pins are connected into a loopback data configuration (see Figure 7). In
this mode, the receiver and transmitter interrupts remain fully operational. The
Modem Control Interrupts are also operational, but the interrupts’ sources are
switched to the lower four bits of the Modem Control. Interrupts continue to be
controlled by the IER register.
logic 0 = disable loopback mode (normal default condition)
logic 1 = enable local loopback mode (diagnostics) MCR[3] OUT2. In the loopback mode this bit is used to control the modem DCD signal
via OUT2.
logic 0 = OUT2 is at logic 1. In the loopback mode, sets OUT2 (DCD)
internally to a logic1.
logic 1 = OUT2 is at logic 0. In the loopback mode, sets OUT2 (DCD)
internally to a logic 0. MCR[2] OUT1, OUT.Inthe loopback mode, thisbitis usedto control modemRI interface
signal via OUT1 (OUT in the HVQFN32 package).
logic 0 = OUT1/OUT is at logic 1. In the loopback mode, sets RI internally to
logic1.
logic 1 = OUT1/OUT is set at logic 0. In the loopback mode, sets RI internally
to logic0. MCR[1] RTS
logic0= force RTS output to a logic 1 (normal default condition)
logic1= force RTS output to a logic0 MCR[0] DTR
logic0= force DTR output to a logic 1 (normal default condition)
logic1= force DTR output to a logic0
Table 19. Modem Control Register bits description …continued
