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SC16C2552BIA44
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
General descriptionThe SC16C2552B is a two channel Universal Asynchronous Receiver and Transmitter
(UART) used for serial data communications. Its principal function is to convert parallel
data into serial data, and vice versa. The UART can handle serial data rates up to Mbit/s.
The SC16C2552B is pin compatible with the PC16552 and ST16C2552. The
SC16C2552B provides enhanced UART functions with 16-byte FIFOs, modem control
interface, DMA mode data transfer and concurrent writes to control registers of both
channels. The DMA mode data transfer is controlled by the FIFO trigger levels and the
RXRDY and TXRDY signals. On-board status registers provide the user with error
indications and operational status. System interrupts and modem control features maybe
tailored by software to meet specific user requirements. An internal loopback capability
allows on-board diagnostics. Independent programmable baud rate generators are
provided to select transmit and receive baud rates.
The SC16C2552B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range,
and is available in a plastic PLCC44 package.
Features Industrial temperature range (−40 °C to +85 °C)5V , 3.3 V and 2.5 V operation Pin-to-pin compatible to PC16C552, ST16C2552 Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5V5 V tolerant on input only pins1 16-byte transmit FIFO 16-byte receive FIFO with error flags Independent transmit and receive UART control Four selectable receive FIFO interrupt trigger levels; fixed transmit FIFO interrupt
trigger level Modem control functions (CTS, RTS, DSR, DTR, RI, CD) DMA operation and DMA monitoring via package I/O pins, TXRDY/RXRDY UART internal register sections A and B may be written to concurrently Multi-function output allows more package functions with fewer I/O pins Programmable character lengths (5, 6, 7, 8), with even, odd, or no parity
SC16C2552B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte
FIFOs
Rev. 03 — 12 February 2009 Product data sheet For data bus pins D7 to D0, see Table 23 “Limiting values”.
NXP Semiconductors SC16C2552B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Ordering information Block diagram
Table 1. Ordering informationSC16C2552BIA44 PLCC44 plastic leaded chip carrier; 44 leads SOT187-2
NXP Semiconductors SC16C2552B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description 10 I
Register select. A0 to A2 are used during read and write operations to select the UART
register to read from or writeto.A1 14 I 15 I
CDA42 I
Carrier detect A, B (active LOW). These inputs are associated with individual UART
channelsA throughB.A logic0on this pin indicates thata carrier has been detectedby the
modem for that channel.CDB 30 I
CHSEL 16 I
Channel select. UART channelAorBis selectedby the logic stateof this pin when CSisa
logic 0. A logic 0 on CHSEL selects the UART channel B, while a logic 1 selects UART
channel A. Bit 0 of AFR register can temporarily override CHSEL function, allowing user to
write to both channel registers simultaneously with one write cycle.
CTSA 40 I
Clear to Send A, B (active LOW). These inputs are associated with individual UART
channelsA throughB.A logic0onthe CTSnpin indicates the modemor datasetis readyto
accept transmit data from the SC16C2552B. Status can be tested by reading MSR[4].CTSB 28 I 18 I
Chip select (active LOW). This function selects channelAor channelBin accordance with
the logical stateofthe CHSEL pin. This allows datatobe transferred between the user CPU
and the SC16C2552B.
NXP Semiconductors SC16C2552B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 2 I/O
Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring
information to or from the controlling CPU.D1 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O
DSRA 41 I
Data Set Ready A, B (active LOW). These inputs are associated with individual UART
channels A through B. A logic 0 on this pin indicates the modem or data set is powered-on
and is ready for data exchange with the UART.DSRB 29 I
DTRA 37 O
Data Terminal Ready A, B (active LOW). These outputs are associated with individual
UART channels A through B. A logic 0 on this pin indicates that the SC16C2552B is
powered-on and ready. This pin can be controlled via the modem control register. Writing a
logic1to MCR[0] will set the DTRn outputto logic0, enabling the modem. This pinwillbea
logic 1 after writing a logic 0 to MCR[0], or after a reset.
DTRB 27 O
GND 12, 22 I
Signal and power ground.INTA 34 O
InterruptA,B (active HIGH). This functionis associated with individual channel interrupts.
Interrupts are enabled in the Interrupt Enable Register (IER). Interrupt conditions include:
receiver errors, available receiver buffer data, transmit buffer empty, or when a modem
status flag is detected.
INTB 17 O
IOR 24 I
Read strobe (active LOW). A logic 0 transition on this pin will load the contents of an
internal register defined by address bits A[2:0] onto the SC16C2552B data bus (D[7:0]) for
access by external CPU.
IOW20 I
Write strobe (active LOW). A logic 0 transition on this pin will transfer the contents of the
data bus (D[7:0]) from the external CPUtoan internal register thatis definedby address bits
A[2:0].
MFA35 O
Multi-functionA,B. This functionis associated withan individual channel function,AorB.
User programmable bits 2:1 of the Alternate Function Register (AFR) selects a signal
functionor outputon these pins. OP2 (interrupt enable), BAUDOUT, and RXRDY are signal
functions that maybe selectedby the AFR. These signal functions are describedas follows:
OP2. When OP2 is selected, the MFn pin is a logic 0 when MCR[3] is set to a logic1. logic 1 is the default signal condition that is available following a master reset or
power-up.
BAUDOUT. When BAUDOUT function is selected, the 16× baud rate clock output is
available at this pin.
RXRDY. RXRDYis primarily intendedfor monitoring DMA mode1 transfersfor the receive
data FIFOs. A logic 0 indicates there is receive data to read/unload, i.e., receive ready
status with one or more RX characters available in the FIFO/RHR. This pin is a logic1
when the FIFO/RHR is empty or when the programmed trigger level has not been
reached. This signal can also be used for single mode transfers (DMA mode0).
MFB 19 O
RESET 21 I
Reset (active HIGH).A logic1on thispin will reset the internal registers andallthe outputs.
The UART transmitter output and the receiver input will be disabled during reset time. See
Section 7.11 “SC16C2552B external reset condition” for initialization details.
RIA 43 I
Ring Indicator A, B (active LOW). These inputs are associated with individual UARTchannels A through B. A logic 0 on this pin indicates the modem has received a ringing
signal from the telephone line.A logic1 transitionon this inputpin will generatean interrupt
if modem status interrupt is enabled.
RIB 31 I
Table 2. Pin description …continued
NXP Semiconductors SC16C2552B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOsRTSA 36 O
Request to Send A, B (active LOW). These outputs are associated with individual UART
channels A through B. A logic 0 on the RTSn pin indicates the transmitter is ready to
transmit data. Writing a logic 1 in the modem control register MCR[1] will set this pin to a
logic 0, indicating that the transmitter is ready to transmit data. After a reset, this pin will be
set to a logic1.
RTSB 23 O
RXA 39 I
Receive data A, B. These inputs are associated with individual serial channel data to the
SC16C2552B receive input circuits A through B. The RXn signal will be a logic 1 during
reset, idle (no data). Duringthe local Loopback mode, the RXn inputpinis disabled and TXn
data is connected to the UART RXn input, internally.
RXB 25 I
TXA 38 O
Transmit data A, B. These outputs are associated with individual serial transmit channel
data from the SC16C2552B. The TXn signal will be a logic 1 during reset, idle (no data), or
when the transmitter is disabled. During the local Loopback mode, the TXn output pin is
disabled and TXn data is internally connected to the UART RXn input.
TXB 26 O
TXRDYA1 O
Transmit Ready A, B (active LOW). These outputs provide the TX FIFO/THR status for
individual transmit channels (A, B). TXRDYn is primarily intended for monitoring
DMA mode 1 transfers for the transmit data FIFOs. An individual channel’s TXRDYA,
TXRDYB buffer ready status is indicated by logic 0, i.e., at least one location is empty and
available in the FIFO or THR. This signal can also be used for single mode transfers (DMA
mode0).
TXRDYB 32 O
VCC 33, 44 I
Power supply input.XTAL1 11 I
Crystal or external clock input. Functions as a crystal input or as an external clock input. crystal canbe connected between thispin andXTAL2to forman internal oscillator circuit.
Alternatively, an external clock can be connected to this pin to provide custom data rates.
See Section 6.5 “Programmable baud rate generator”.
XTAL2 13 O
Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal oscillator
output or buffered clock output. Should be left open if an external clock is connected to
XTAL1.
Table 2. Pin description …continued
NXP Semiconductors SC16C2552B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Functional descriptionThe SC16C2552B provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessaryfor converting the serial data stream into
parallel data that is required with digital data systems. Synchronization for the serial data
stream is accomplished by adding start and stop bits to the transmit data to form a data
character. Data integrity is ensured by attaching a parity bit to the data character. The
parity bit is checked by the receiver for any transmission bit errors. The SC16C2552B is
fabricated with an advanced CMOS process.
The SC16C2552B is an upward solution that provides a dual UART capability with bytes of transmit and receive FIFO memory, instead of none in the 16C450. The
SC16C2552B is designed to work with high speed modems and shared network
environments that require fast data processing time. Increased performanceis realizedin
the SC16C2552Bby the transmit and receive FIFOs. This allows the external processorto
handle more networking tasks within a given time. In addition, the four selectable receive
FIFO trigger interrupt levels are uniquely provided for maximum data throughput
performance, especially when operating in a multi-channel environment. The FIFO
memory greatly reduces the bandwidth requirement of the external controlling CPU,
increases performance, and reduces power consumption.
The SC16C2552B is capable of operation up to 1.5 Mbit/s with a 24 MHz crystal. With a
crystal or external clock input of 7.3728 MHz, the user can select data rates up to
460.8 kbit/s.
The rich feature setof the SC16C2552Bis available through internal registers. Selectable
receive FIFO trigger levels, selectable TX and RX baud rates, and modem interface
controls are all standard features.
6.1 UART A-B functionsThe UART provides the user with the capability to bidirectionally transfer information
between an external CPU, the SC16C2552B package, and an external serial device. A
logic 0 on chip select pin CS and a logic 1 on CHSEL allows the user to configure, send
data, and/or receive data via UART channel A. A logic 0 on chip select pin CS and a
logic 0 on CHSEL allows the user to configure, send data, and/or receive data via UART
channel B. Individual channel select functions are shown in Table3.
During a write mode cycle, the setting of AFR[0] to a logic 1 will override the CHSEL
selection and allow a simultaneous write to both UART channel sections. This functional
capability allows the registers in both UART channels to be modified concurrently, saving
individual channel initialization time. Caution should be considered, however, when using
this capability. Any in-process serial data transfer maybe disruptedby changingan active
channel’s mode.
Table 3. Serial port selection=1 none=0 UART channel selected as follows:
CHSEL= 1: UART channel A
CHSEL= 0: UART channel B
NXP Semiconductors SC16C2552B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
6.2 Internal registersThe SC16C2552B provides two sets of internal registers (A and B) consisting of registers each for monitoring and controlling the functions of each channel of the
UART. These registers are shownin Table4. The UART registers functionas data holding
registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control
register (FCR), line status and control registers (LCR/LSR), modem status and control
registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), a
user accessible scratchpad register (SPR), and an Alternate Function Register (AFR).
[1] The baud rate register and AFR register sets are accessible only when CS is a logic 0 and LCR[7] is a
logic 1 for the register set (A/B) being accessed.
6.3 FIFO operationThe 16 byte transmit and receive data FIFOs are enabled by the FIFO Control Register
(FCR) bit 0. The user can set the receive trigger level via FCR[7:6], but not the transmit
trigger level. The receiver FIFO section includes a time-out function to ensure data is
delivered to the external CPU. A time-out interrupt is generated whenever the Receive
Holding Register (RHR) has not been read following the loading of a character, or the
receive trigger interrupt is generated when RX FIFO level is equal to the program RX
trigger value.
6.4 Time-out interruptsThe interrupts are enabled by IER[3:0]. Care must be taken when handling these
interrupts. Following a reset, if the transmitter interrupt is enabled, the SC16C2552B will
issuean interruptto indicate that the Transmit Holding Registeris empty. The ISR register
provides the current singular highest priority interrupt only. A condition can exist where a
higher priority interrupt may mask the lower priority interrupt(s). Only after servicing the
higher pending interrupt will the lower priority interrupt(s) be reflected in the status
register. Servicing the interrupt without investigating further interrupt conditions can result
in data errors.
Table 4. Internal registers decoding
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR) 0 0 Receive Holding Register Transmit Holding Register 0 1 Interrupt Enable Register Interrupt Enable Register 1 0 Interrupt Status Register FIFO Control Register 1 1 Line Control Register Line Control Register 0 0 Modem Control Register Modem Control Register 0 1 Line Status Register n/a 1 0 Modem Status Register n/a 1 1 Scratchpad Register Scratchpad Register
Baud rate register set (DLL/DLM, AFR)[1] 0 0 LSB of Divisor Latch LSB of Divisor Latch 0 1 MSB of Divisor Latch MSB of Divisor Latch 1 0 Alternate Function Register Alternate Function Register
NXP Semiconductors SC16C2552B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOsWhen two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time-Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the SC16C2552B
FIFO may hold more characters than the programmed trigger level. Following the removal
of a data byte, the user should re-check LSR[0] for additional characters. A Receive
Time-Out will not occur if the receive FIFO is empty. The time-out counter is reset at the
center of each stop bit received or each time the receive holding register (RHR) is read.
The actual time-out value is 4 character time.
6.5 Programmable baud rate generatorThe SC16C2552B supports high speed modem technologies that have increased input
data rates by employing data compression schemes. For example, a 33.6 kbit/s modem
that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s
ISDN modem that supports data compression may needan input data rateof 460.8 kbit/s.
A baud rate generator is provided for each UART channel, allowing independent TX/RX
channel control. The programmable Baud Rate Generator (BRG) is capable of accepting
an input clock up to 80 MHz, as required for supporting a 5 Mbit/s data rate. The
SC16C2552B canbe configuredfor internalor external clock operation. For internal clock
oscillator operation, an industry standard microprocessor crystal is connected externally
between the XT AL1 and XTAL2 pins. Alternatively, an external clock can be connected to
the XTAL1 pin to clock the internal baud rate generator for standard or custom rates (see
Table 5).
The generator divides the input 16× clock by any divisor from 1 to (216− 1). The
SC16C2552B divides the basic external clock by 16. The basic 16× clock provides table
rates to support standard and custom applications using the same system design. The
rate tableis configured via the DLL and DLM internal register functions. Customized baud
rates can be achieved by selecting the proper divisor values for the MSB and LSB
sections of baud rate generator.
Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a
user capabilityfor selecting the desired final baud rate. The examplein Table5 shows the
selectable baud rate table available when using a 1.8432 MHz external clock input.
NXP Semiconductors SC16C2552B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
6.6 DMA operationThe SC16C2552B FIFO trigger level provides additional flexibility to the user for block
mode operation. LSR[6:5] provide an indication when the transmitter is empty or has an
empty location(s). The user can optionally operate the transmit and receive FIFOs in the
DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA
mode is de-activated (DMA Mode 0), the SC16C2552B activates the interrupt output pin
for each data transmitor receive operation. When DMA modeis activated (DMA Mode1),
the user takes the advantageof block mode operationby loadingor unloading the FIFOin
a block sequence determined by the receive trigger level and the transmit FIFO. In this
mode, the SC16C2552B sets the interrupt output pin when characters in the transmit
FIFO is below 16, or the characters in the receive FIFOs are above the receive trigger
level.
6.7 Loopback modeThe internal loopback capability allows on-board diagnostics. In the Loopback mode, the
normal modem interface pins are disconnected and reconfigured for loopback internally.
MCR[3:0] register bits are used for controlling loopback diagnostic testing. In the
Loopback mode, INT enable and MCR[2]in the MCR register (bits 3:2) control the modem
RI and CD inputs, respectively. MCR signals DTR (bit 0) and RTS (bit 1) are used to
control the modem DSR and CTS inputs, respectively. The transmitter output (TX) and the
receiver input (RX) are disconnected from their associated interface pins, and instead are
connected together internally (see Figure 4). The CTS, DSR, CD, and RI are
disconnected from their normal modem control inputs pins, and instead are connected
internally to RTS, DTR, OP2 and OP1. Loopback test data is entered into the transmit
holding register via the user data bus interface, D0to D7. The transmit UART serializes
the data and passes the serial data to the receive UART via the internal loopback
connection. The receive UART converts the serial data back into parallel data thatis then
Table 5. Baud rate generator programming table using a 1.8432 MHz clock 2304 900 09 00 1536 600 06 00
150 768 300 03 00
300 384 180 01 80
600 192 C0 00 C0
1200 96 60 00 60
2400 48 30 00 30
4800 24 18 00 18
7200 16 10 00 10
9600 12 0C 00 0C
19.2k 6 06 00 06
38.4k 3 03 00 03
57.6k 2 02 00 02
115.2k 1 01 00 01
NXP Semiconductors SC16C2552B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOsmade available at the user data interface D0to D7. The user optionally compares the
received data to the initial transmitted data for verifying error-free operation of the UART
TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational. However, the interrupts can only be read using
lower four bitsof the Modem Status Register (MSR[3:0]) insteadof the four Modem Status
Register bits 7:4. The interrupts are still controlled by the IER.
NXP Semiconductors SC16C2552B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Register descriptionsTable 6 details the assigned bit functions for the SC16C2552B internal registers. The
assigned bit functions are further defined in Section 7.1 through Section 7.11.
[1] The value shown represents the register’s initialized hexadecimal value; X= not applicable.
[2] The ‘General register set’ registers are accessible only when CS is a logic 0 and LCR[7] is logic0.
[3] The Baud rate register and AFR register sets are accessible only when CS is a logic 0 and LCR[7] is a logic1.
Set A is accessible when CHSEL is a logic 1, and Set B is accessible when CHSEL is a logic0.
Table 6. SC16C2552B internal registers
General register set[2]
Special register set[3]
NXP Semiconductors SC16C2552B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR)The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writingto the THR transfers the contentsof the data bus (D7 through D0)
to the TSR and UART via the THR, providing that the THR is empty. The THR empty flag the LSR[5] register willbe settoa logic1 when the transmitteris emptyor when datais
transferred to the TSR.
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a
Receive Serial Shift Register (RSR). Receive datais removed from the SC16C2552B and
receive FIFO by reading the RHR register. The receive section provides a mechanism to
prevent false starts. On the falling edge of a start or false start bit, an internal receiver
counter starts counting clocks at the 16× clock rate. After 71 ⁄2 clocks, the start bit time
shouldbe shiftedto the centerof the start bit.At this time the startbitis sampled, andifit
is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver
from assembling a false character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INTA, INTB output pins.
Table 7. Interrupt Enable Register bits description7:4 IER[7:4] not used; initialized to logic0 IER[3] Modem Status Interrupt. This interrupt will be issued whenever there is a
modem status change as reflected in MSR[3:0].
logic 0 = disable the Modem Status Register interrupt (normal default
condition)
logic 1 = enable the Modem Status Register interrupt IER[2] Receive Line Status interrupt. This interrupt willbe issued whenevera receive
data error condition exists as reflected in LSR[4:1].
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt IER[1] Transmit Holding Register interrupt.In the 16C450 mode, this interrupt willbe
issued whenever the THRis empty andis associated with LSR[5].In the FIFO
modes, this interrupt will be issued whenever the FIFO and THR are empty.
logic 0 = disable the Transmit Holding Register Empty (TXRDY) interrupt
(normal default condition)
logic 1 = enable the TXRDY (ISR level 3) interrupt IER[0] Receive Holding Register. In the 16C450 mode, this interrupt will be issued
when the RHR has data, or is cleared when the RHR is empty. In the FIFO
mode, this interrupt will be issued when the FIFO has reached the
programmed trigger leveloris cleared when the FIFO drops below the trigger
level.
logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt (normal
default condition)
logic 1 = enable the RXRDY (ISR level 2) interrupt
NXP Semiconductors SC16C2552B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.2.1 IER versus Transmit/Receive FIFO interrupt mode operationWhen the receive FIFO (FCR[0]= logic 1) and receive interrupts (IER[0]= logic 1) are
enabled, the receive interrupts and register status will reflect the following:
The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU
when the receive FIFO has reached the programmed trigger level. It will be cleared
when the receive FIFO drops below the programmed trigger level.
Receive FIFO status will also be reflected in the user accessible ISR register when
the receive FIFO trigger level is reached. Both the ISR register receive status bit and
the interrupt will be cleared when the FIFO drops below the trigger level.
The receive data ready bit (LSR[0]) is set as soon as a character is transferred from
the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.
When the Transmit FIFO and interrupts are enabled, an interrupt is generated when
the transmit FIFOis empty dueto the unloadingof the databy the TSR and UARTfor
transmission via the transmission media. The interruptis cleared eitherby reading the
ISR register or by loading the THR with new data characters.
7.2.2 IER versus Receive/Transmit FIFO polled mode operationWhen FCR[0]= logic 1, resetting IER[3:0] enables the SC16C2552B in the FIFO polled
mode of operation. In this mode, interrupts are not generated and the user must poll the
LSR register for TX and/or RX data status. Since the receiver and transmitter have
separate bits in the LSR either or both can be used in the polled mode by selecting
respective transmit or receive control bit(s).
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[4:1] will provide the type of receive errors or a receive break, if encountered.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.
LSR[7] will show if any FIFO data errors occurred.
NXP Semiconductors SC16C2552B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.3 FIFO Control Register (FCR)This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels and select the DMA mode.
7.3.1 DMA mode
7.3.1.1 Mode 0 (FCR bit 3 = 0)Set and enable the interrupt for each single transmit or receive operation and is similar to
the 16C450 mode. T ransmit Ready (TXRDY) will go to a logic 0 whenever an empty
transmit space is available in the Transmit Holding Register (THR). Receive Ready
(RXRDY)at the MFn pin willgotoa logic0 whenever the Receive Holding Register (RHR)
is loaded with a character and AFR[2:1] is set to the RXRDY mode.
7.3.1.2 Mode 1 (FCR bit 3 = 1)Set and enable the interruptina block mode operation. The transmit interruptis set when
the transmit FIFO has at least one empty location. TXRDY remains a logic 0 as long as
one empty FIFO location is available. The receive interrupt is set when the receive FIFO
fills to the programmed trigger level. However, the FIFO continues to fill regardless of the
programmed level until the FIFO is full. RXRDY at the MFn pin remains a logic 0 as long
as the FIFO fill level is above the programmed trigger level, and AFR[2:1] is set to the
RXRDY mode.
7.3.2 FIFO mode
Table 8. FIFO Control Register bits description7:6 FCR[7:6] RCVR trigger. These bits are usedtoset the trigger levelfor the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However,the FIFO will continueto
be loaded until it is full. Refer to Table9.
5:4 FCR[5:4] Not used; initialized to logic0. FCR[3] DMA mode select.
logic 0 = set DMA mode ‘0’ (normal default condition)
logic 1 = set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C2552B is in the16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode
(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there
areno charactersin the transmit FIFOor Transmit Holding Register,the
TXRDYn pin will be a logic 0. Once active, the TXRDYn pin will go to a
logic 1 after the first character is loaded into the Transmit Holding
Register.
Receive operation in mode ‘0’: When the SC16C2552B is in 16C450mode, or in the FIFO mode (FCR[0]= logic 1; FCR[3]= logic 0) and
thereisat least one characterin the receive FIFO, the RXRDY signalat
the MFn pin will be a logic 0. Once active, the RXRDY signal at the
MFn pin will go to a logic 1 when there are no more characters in the
receiver. Note that the AFR register must be set to the RXRDY mode
prior to any possible reading of the RXRDY signal.
NXP Semiconductors SC16C2552B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs(continued)
Transmit operation in mode ‘1’: When the SC16C2552B is in FIFOmode (FCR[0] = logic 1; FCR[3]= logic 1), the TXRDYn pin will be a
logic 1 when the transmit FIFO is completely full. It will be a logic0 if
one or more FIFO locations are empty.
Receive operation in mode ‘1’: When the SC16C2552B is in FIFOmode (FCR[0]= logic1; FCR[3]= logic1) and the trigger level has been
reached,ora Receive Time-out has occurred, the RXRDY signalat the
MFn pin will go to a logic 0. Once activated, it will go to a logic 1 after
there are no more characters in the FIFO. Note that the AFR register
must be set to the RXRDY mode prior to any possible reading of the
RXRDY signal. FCR[2] XMIT FIFO reset.
logic 0 = no FIFO transmit reset (normal default condition)
logic1= clears the contentsofthe transmit FIFO and resets the FIFO
counter logic (the Transmit Shift Register is not cleared or altered).
This bit will return to a logic 0 after clearing the FIFO. FCR[1] RCVR FIFO reset.
logic 0 = no FIFO receive reset (normal default condition)
logic1= clears the contentsof the receive FIFO and resets the FIFO
counter logic (the Receive Shift Register is not cleared or altered).
This bit will return to a logic 0 after clearing the FIFO. FCR[0] FIFOs enabled.
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic1= enable the transmit and receive FIFO.
Thisbit mustbea‘1’
when other FCR bits are written to or they will not be
programmed.
Table 9. RCVR trigger levelsTable 8. FIFO Control Register bits description …continued
NXP Semiconductors SC16C2552B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.4 Interrupt Status Register (ISR)The SC16C2552B provides four levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with four
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged until
the pending interrupt is serviced. Whenever the interrupt status register is read, the
interrupt status is cleared. However, it should be noted that only the current pending
interrupt is cleared by the read. A lower level interrupt may be seen after re-reading the
interrupt status bits. Table 10 shows the data values (bits 3:0) for the four prioritized
interrupt levels and the interrupt sources associated with each of these interrupt levels.
Table 10. Interrupt source 0 1 1 0 LSR (Receiver Line Status Register) 0 1 0 0 RXRDY (Received Data Ready) 1 1 0 0 RXRDY (Receive Data Time-out) 0 0 1 0 TXRDY (Transmitter Holding Register empty) 0 0 0 0 MSR (Modem Status Register)
Table 11. Interrupt Status Register bits description7:6 ISR[7:6] FIFOs enabled. These bits are settoa logic0 when the FIFOs are not being
used in the 16C450 mode. They are set to a logic 1 when the FIFOs are
enabled in the SC16C2552B mode.
logic 0 or cleared = default condition
5:4 ISR[5:4] not used; initialized to a logic0
3:1 ISR[3:1] INT priority bits. These bits indicate the source for a pending interrupt at
interrupt priority levels 1, 2 and 3 (see Table 10). ISR[0] INT status.
logic 0 = an interrupt is pending and the ISR contents may be used as a
pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
NXP Semiconductors SC16C2552B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.5 Line Control Register (LCR)The Line Control Register is used to specify the asynchronous data communication
format. The word length, the numberof stop bits and the parity are selectedby writing the
appropriate bits in this register.
Table 12. Line Control Register bits description LCR[7] Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
logic0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled LCR[6] Set break. When enabled, the Break controlbit causesa break condition
to be transmitted (the TX output is forced to a logic 0 state). This
condition exists until disabled by setting LCR[6] to a logic0.
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
5:3 LCR[5:3] Programs the parity conditions (see Table 13) LCR[2] Stop bits. The length of stop bit is specified by this bit in conjunction with
the programmed word length (see Table 14).
logic 0 or cleared = default condition
1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see Table 15).
logic 0 or cleared = default condition
Table 13. LCR[5:3] parity selection X 0 no parity 0 1 odd parity 1 1 even parity 0 1 forced parity ‘1’ 1 1 forced parity ‘0’
Table 14. LCR[2] stop bit length 5, 6, 7, 8 1 11⁄2 6, 7, 8 2
Table 15. LCR[1:0] word length118
NXP Semiconductors SC16C2552B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.6 Modem Control Register (MCR)This register controls the interface with the modem or a peripheral device.
Table 16. Modem Control Register bits description7:5 MCR[7:5] reserved; initialized to a logic0 MCR[4] Loopback. Enable the local Loopback mode (diagnostics).In this modethe
transmitter output (TX) and the receiver input (RX), CTS, DSR, CD andRI
are disconnected from the SC16C2552B I/O pins. Internally the modem
data and control pins are connected into a loopback data configuration
(see Figure4).In this mode, the receiver and transmitter interrupts remain
fully operational. The modem control interrupts are also operational, but
the interrupts’ sources are switched to the lower four bits of the Modem
Control. Interrupts continue to be controlled by the IER register.
logic 0 = disable Loopback mode (normal default condition)
logic 1 = enable local Loopback mode (diagnostics) MCR[3] OP2. Used to control the modem CD signal in the Loopback mode.
logic 0 = sets OP2 to a logic 1 (normal default condition). In the
Loopback mode, sets CD internally to a logic1.
logic1= sets OP2toa logic0.In the Loopback mode, sets CD internally
to a logic0. MCR[2] OP1. This bit is used in the Loopback mode only. In the Loopback mode,
this bit is used to write the state of the modem RI interface signal. MCR[1] RTS
logic0 = force RTS output to a logic 1 (normal default condition)
logic1= force RTS output to a logic0 MCR[0] DTR
logic0 = force DTR output to a logic 1 (normal default condition)
logic 1 = force DTR output to a logic0
NXP Semiconductors SC16C2552B
5 V , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.7 Line Status Register (LSR)This register provides the status of data transfers between the SC16C2552B and
the CPU.
Table 17. Line Status Register bits description LSR[7] FIFO data error.
logic 0 = no error (normal default condition)
logic 1 = at least one parity error, framing error or break indication is in the
current FIFO data. This bit is cleared when RHR register is read. LSR[6] THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a
logic 1 whenever the Transmit Holding Register and the T ransmit Shift Register
are both empty. It is reset to logic 0 whenever either the THR or TSR contains a
data character.In the FIFO mode, thisbitis setto logic1 whenever the Transmit
FIFO and Transmit Shift Register are both empty. LSR[5] THR empty. This bit is the Transmit Holding Register Empty indicator. This bit
indicates that the UART is ready to accept a new character for transmission. In
addition, this bit causes the UART to issue an interrupt to CPU when the THR
interrupt enable is set. The THR bit is set to a logic 1 when a character is
transferred from the Transmit Holding Register into the Transmit Shift Register.
The bit is reset to a logic 0 concurrently with the loading of the Transmit Holding
Registerby the CPU.In the FIFO mode, thisbitis set when the transmit FIFOis
empty; it is cleared when at least 1 byte is written to the transmit FIFO. LSR[4] Break interrupt.
logic 0 = no break condition (normal default condition)
logic 1 = the receiver received a break signal (RX was a logic 0 for one
character frame time). In the FIFO mode, only one break character is loaded
into the FIFO. LSR[3] Framing error.
logic 0 = no framing error (normal default condition)
logic1= framing error. The receive character didnot havea valid stop bit(s).In
the FIFO mode, this error is associated with the character at the top of the
FIFO. LSR[2] Parity error.
logic 0 = no parity error (normal default condition
logic 1 = parity error. The receive character does not have correct parity
information andis suspect.In the FIFO mode, this erroris associated with the
character at the top of the FIFO. LSR[1] Overrun error.
logic0 = no overrun error (normal default condition)
logic1= overrun error. A data overrun error occurred in the Receive Shift
Register. This happens when additional data arrives while the FIFO is full. In
this case, the previous datain the shift registeris overwritten. Note that under
this condition, the data bytein the Receive Shift Registerisnot transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error. LSR[0] Receive data ready.
logic0 = no data in Receive Holding Register or FIFO (normal default
condition)
logic1= data has been received andis savedin the Receive Holding Register
or FIFO
