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PKD01EP-PKD01FP
Monolithic Peak Detector with Reset-and-Hold Mode
REV.A
Monolithic Peak Detector
with Reset-and-Hold Mode
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Monolithic Design for Reliability and Low Cost
High Slew Rate: 0.5 V/�s
Low Droop Rate
TA = 25�C: 0.1 mV/ms
TA = 125�C: 10 mV/ms
Low Zero-Scale Error: 4 mV
Digitally Selected Hold and Reset Modes
Reset to Positive or Negative Voltage Levels
Logic Signals TTL and CMOS Compatible
Uncommitted Comparator On-Chip
Available in Die Form
GENERAL DESCRIPTIONThe PKD01 tracks an analog input signal until a maximum
amplitude is reached. The maximum value is then retained as a
peak voltage on a hold capacitor. Being a monolithic circuit, the
PKD01 offers significant performance and package density
advantages over hybrid modules and discrete designs without
sacrificing system versatility. The matching characteristics
attained in a monolithic circuit provide inherent advantages
when charge injection and droop rate error reduction are
primary goals.
Innovative design techniques maximize the advantages of mono-
lithic technology. Transconductance (gm) amplifiers were chosen
over conventional voltage amplifier circuit building blocks. The
gm amplifiers simplify internal frequency compensation, minimize
acquisition time and maximize circuit accuracy. Their outputs
are easily switched by low glitch current steering circuits. The
steered outputs are clamped to reduce charge injection errors
upon entering the hold mode or exiting the reset mode. The inher-
ently low zero-scale error is further reduced by active Zener-Zap
trimming to optimize overall accuracy.
The output buffer amplifier features an FET input stage to
reduce droop rate error during lengthy peak hold periods. A bias
current cancellation circuit minimizes droop error at high ambi-
ent temperatures.
Through the DET control pin, new peaks may either be detected
or ignored. Detected peaks are presented as positive output
levels. Positive or negative peaks may be detected without
additional active circuits, since Amplifier A can operate as an
inverting or noninverting gain stage.
An uncommitted comparator provides many application options.
Status indication and logic shaping/shifting are typical examples.
PKD01–SPECIFICATIONS
ELECTRICAL CHARACTERISTICSDIGITAL INPUTS – RST, DET
NOTESGuaranteed by design.DET = 1, RST = 0.Due to limited production test times, the droop current corresponds to junction temperature (TJ). The droop current vs. time (after power-on) curve clarified this point. Since
most devices (in use) are on for more than 1 second, ADI specifies droop rate for ambient temperature (TA) also. The warmed-up (TA) droop current specification is correlated
to the junction temperature (TJ) value. ADI has a droop current cancellation circuit that minimizes droop current at high temperature. Ambient (TA) temperature specifications
are not subject to production testing.
Specifications subject to change without notice.
(@ VS = �15V, CH = 1000 pF, TA = 25�C, unless otherwise noted.)
PKD01
ELECTRICAL CHARACTERISTICSNOTESGuaranteed by design.DET = 1, RST = 0.Due to limited production test times, the droop current corresponds to junction temperature (TJ). The droop current vs. time (after power-on) curve clarifies this
point. Since most devices (in use) are on for more than 1 second, ADI specifies droop rate for ambient temperature (TA) also. The warmed-up (TA) droop current
specification is correlated to the junction temperature (TJ) value. ADI has a droop current cancellation circuit that minimizes droop current at high temperature.
Ambient (TA) temperature specifications are not subject to production testing.
Specifications subject to change without notice.
(@ VS = �15 V, CH = 1000 pF, –55�C ≤ TA ≤ +125�C for PKD01AY, –25�C ≤ TA ≤ +85�C for
PKD01EY, PKD01FY and 0�C ≤ TA ≤ +70�C for PKD01EP, PKD01FP, unless otherwise noted.)
PKD01
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the PKD01 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1, 2Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Input Voltage . . . . . . . . . . . . . . . . . . . Equal to Supply Voltage
Logic and Logic Ground
Voltage . . . . . . . . . . . . . . . . . . . . . . Equal to Supply Voltage
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Amplifier A or B Differential Input Voltage . . . . . . . . . . ±24 V
Comparator Differential Input Voltage . . . . . . . . . . . . . ±24 V
Comparator Output Voltage
. . . . . . . . . . . . . . . . . . . . . . Equal to Positive Supply Voltage
Hold Capacitor Short-Circuit Duration . . . . . . . . . . Indefinite
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300°C
Storage Temperature Range
PKD01AY, PKD01EY, PKD01FY . . . . . –65°C to +150°C
PKD01EP, PKD01FP . . . . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range
PKD01AY . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
PKD01EY, PKD01FY . . . . . . . . . . . . . . . . –25°C to +85°C
PKD01EP, PKD01FP . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Junction Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C
NOTES
1Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS*θJA is specified for worst-case mounting conditions, i.e., θJA is specified for device
in socket for cerdip and PDIP packages.
ORDERING GUIDE1NOTESBurn-in is available on commercial and industrial temperature range parts in
cerdip, plastic DIP, and TO-can packages.For devices processed in total compliance to MIL-STD-883, add /883 after
part number. Consult factory for 883 data sheet.
PIN CONFIGURATION
DICE CHARACTERISTICS
WAFER TEST LIMITSCOMPARATOR
DIGITAL INPUTS–RST, DET
gm AMPLIFIERS A, B
NOTES
1Guaranteed by design.
2DET = 1, RST = 0.
3Due to limited production test times, the droop current corresponds to junction temperature (TJ). The droop current vs. time (after power-on) curve clarifies this
point. Since most devices (in use) are on for more than 1 second, ADI specifies droop rate for ambient temperature (TA) also. The warmed-up (TA) droop current
specification is correlated to the junction temperature (TJ) value. ADI has a droop current cancellation circuit that minimizes droop current at high temperature.
(@ VS = �15 V, CH = 1000 pF, TA = 25�C, unless otherwise noted.)
PKD01
–Typical Performance Characteristics TPC 1.A and B Input Range vs.
Supply Voltage
TPC 4.Input Spot Noise vs.
Frequency
TPC 7.Amplifier A Charge Injec-
tion Error vs. Input Voltage and
Temperature
TPC 2.A and B Amplifiers Offset
Voltage vs. Temperature
TPC 5.Wideband Noise vs.
Bandwidth
TPC 8.Output Voltage Swing vs.
Supply Voltage (Dual Supply
Operation)
TPC 3.A, B IOS vs. Temperature
TPC 6.Amplifier B Charge Injec-
tion Error vs. Input Voltage and
Temperature
TPC 9.Output Voltage vs. Load
Resistance
TPC 10.Output Error vs.
Frequency and Input Voltage
TPC 13.Large-Signal Inverting
Response
TPC 16.Settling Time for +10 V to
0 V Step Input
TPC 11.Settling Response
TPC 14.Large-Signal Noninverting
Response
TPC 17.Small-Signal Open-Loop
Gain/Phase vs. Frequency
TPC 12.Settling Response
TPC 15.Settling Time for –10 V to
0 V Step Input
TPC 18.Channel-to-Channel
Isolation vs. Frequency
PKD01TPC 26.Comparator Output
Response Time (2 kΩ Pull-Up
Resistor, TA = 25°C)
TPC 27.Comparator Output
Response Time (2 kΩ Pull-Up
Resistor, TA = 25°C)
TPC 24.Acquisition of Step Input
TPC 21.Acquisition Time vs.
External Hold Capacitor and
Acquisition Step
TPC 23.Droop Rate vs. Temperature
TPC 20.Droop Rate vs. Time after
Power On
TPC 25.Acquisition of Sine
Wave Peak
TPC 22.Acquisition Time vs. Input
Voltage Step Size
TPC 19.Off Isolation vs. Frequency
TEMPERATURE – �C
OOP RA
TE (mV/sec),
= 1000pF
100500
TPC 28.Input Logic Range vs.
Supply Voltage
TPC 31.Supply Current vs. Supply
Voltage
TPC 34.Comparator Offset Voltage
vs. Temperature
TPC 29.Input Range of Logic
Ground vs. Supply Voltage
TPC 32.Hold Mode Power Supply
Rejection vs. Frequency
TPC 35.Comparator IOS vs.
Temperature
TPC 30.Logic Input Current vs.
Logic Input Voltage
TPC 33.Comparator Input Bias
Current vs. Differential Input Voltage
TPC 36.Comparator IB vs.
Temperature
