MM74C89N ,64-Bit 3-STATE Random Access Read/Write MemoryMM54C89/MM74C8964-BitTRI-STATERandomAccessRead/WriteMemoryMarch1988MM54C89/MM74C8964-BitTRI-STATEÉR ..
MM74C901N ,Hex Inverting TTL Buffer . Hex Non-Inverting TTL BufferMM74C901 • MM74C902 Hex Inverting TTL Buffer • Hex Non-Inverting TTL BufferOctober 1987Revised Janu ..
MM74C902M ,Hex Non-Inverting TTL BufferElectrical Characteristics” providesconditions for actual device operation.(Soldering, 10 seconds) ..
MM74C902N ,Hex Non-Inverting TTL BufferMM74C902 Hex Non-Inverting TTL BufferOctober 1987Revised January 2004MM74C902Hex Non-Inverting TTL ..
MM74C905N ,3 V to 15 V, 12-bit successive approximation registerMM74C905 12-Bit Successive Approximation RegisterOctober 1987Revised July 2003MM74C90512-Bit Succes ..
MM74C906M ,Hex Open Drain N-Channel BuffersMM74C906 Hex Open Drain N-Channel BuffersOctober 1987Revised January 2004MM74C906Hex Open Drain N-C ..
MN35502 ,For Video稟udiofeatures a built-in digital filter with 16/20-bit input.LRCK 2 27 RSBUPIt uses pulse edge modulatio ..
MN35503 ,For Video稟udioFeatures OUT1D 13 16 OUT2D2 Built-in 8-fold oversampling digital filter using I S bus AV 14 15 AVSS ..
MN3610 ,Image Pickup DevicesFeatures ø 4 19 øR 2A• 2048 floating photodiodes and n-channel buried type CCD shift ø 5 18 NC1Breg ..
MN3610H ,Image Pickup DevicesAbsolute Maximum Ratings (Ta=25˚C, V =0V)SSParameter Symbol Rating UnitVPower supply voltage DD – 0 ..
MN3611 ,Image Pickup DevicesFeatures ø 4 19 øR 2• 2160 floating photodiodes and n-channel buried type CCD shiftNC 5 18 NCregist ..
MN3611RE ,Image Pickup DevicesAbsolute Maximum Ratings (Ta=25˚C, VSS=0V)Parameter Symbol Rating UnitVDDPower supply voltage – 0.3 ..
MM74C89N
64-Bit 3-STATE Random Access Read/Write Memory
MM74C89 64-Bit 3-STATE Random Access Read/Write Memory October 1987 Revised January 1999 MM74C89 64-Bit 3-STATE Random Access Read/Write Memory Read Operation: The complement of the information General Description which was written into the memory is non-destructively The MM74C89 is a 16-word by 4-bit random access read/ read out at the four outputs. This is accomplished by write memory. Inputs to the memory consist of four address selecting the desired address and bringing memory enable lines, four data input lines, a write enable line and a mem- LOW and write enable HIGH. ory enable line. The four binary address inputs are When the device is writing or disabled the output assumes decoded internally to select each of the 16 possible word a 3-STATE (Hi-z) condition. locations. An internal address register latches the address information on the positive to negative transition of the Features memory enable input. The four 3-STATE data output lines working in conjunction with the memory enable input pro- � Wide supply voltage range: 3.0V to 15V vide for easy memory expansion. � Guaranteed noise margin: 1.0V Address Operation: Address inputs must be stable t SA � High noise immunity: 0.45 V (typ.) CC prior to the positive to negative transition of memory � Low power TTL compatibility: enable. It is thus not necessary to hold address information fan out of 2 driving 74L stable for more than t after the memory is enabled (posi- HA tive to negative transition of memory enable). � Low power consumption: 100 nW/package (typ.) � Fast access time: 130 ns (typ.) at V = 10V Write Operation: Information present at the data inputs is CC written into the memory at the selected address by bringing � 3-STATE output write enable and memory enable LOW. Note: The timing is different than the DM7489 in that a positive to negative transition of the memory enable must occur for the memory to be selected. Ordering Code: Order Number Package Number Package Description MM74C89N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Connection Diagram Truth Table ME WE Operation Condition of Outputs Pin Assignments for DIP LL Write 3-STATE L H Read Complement of Selected Word H L Inhibit, Storage 3-STATE H H Inhibit, Storage 3-STATE Top View © 1999 DS005888.prf
