MAX12527ETK+ ,Dual, 65Msps, 12-Bit, IF/Baseband ADCApplications(Msps) (Bits)IF and Baseband Communication ReceiversMAX12557 65 14Cellular, LMDS, Point ..
MAX1253BEUE ,Stand-Alone, 10-Channel, 12-Bit System Monitors with Internal Temperature Sensor and VDD MonitorELECTRICAL CHARACTERISTICS(V = +2.7V to +3.6V (MAX1253), V = +4.5V to +5.5V (MAX1254), V = +2.5V (M ..
MAX1253BEUE+T ,Stand-Alone, 10-Channel, 12-Bit System Monitors with Internal Temperature Sensor and VDD MonitorApplications Ordering InformationSystem SupervisionPART TEMP RANGE PIN-PACKAGERemote Telecom Networ ..
MAX1254BEUE ,Stand-Alone, 10-Channel, 12-Bit System Monitors with Internal Temperature Sensor and VDD MonitorApplications Ordering InformationSystem SupervisionPART TEMP RANGE PIN-PACKAGERemote Telecom Networ ..
MAX12555ETL+ ,14-Bit, 95Msps, 3.3V ADCfeatures a 300µW power-down mode to ±0.35V to ±1.10Vconserve power during idle periods.♦ Common-Mod ..
MAX12557ETK ,Dual, 65Msps, 14-Bit, IF/Baseband ADCApplications(Msps) (Bits)IF and Baseband Communication ReceiversMAX12557 65 14Cellular, LMDS, Point ..
MAX3679CTJ+ , 3.3V, Low-Jitter Crystal to LVPECL Clock Generator
MAX367CWN ,Signal-Line Circuit ProtectorsGeneral Description ________
MAX367EWN ,Signal-Line Circuit ProtectorsFeaturesThe MAX366 and MAX367 are multiple, two-terminal circuit' ±40V Overvoltage Protectionprotec ..
MAX367EWN ,Signal-Line Circuit ProtectorsApplicationsMAX367 available after January 1, 1995.* Dice are tested at T = +25°C only.Process Cont ..
MAX367EWN+ ,Signal Line Circuit Protector with Three Independent ProtectorsMAX366/MAX36719-0326; Rev 0; 12/94Signal-Line Circuit Protectors_______________
MAX3680EAI ,+3.3V / 622Mbps / SDH/SONET 1:8 Deserializer with TTL OutputsELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, T = -40°C to +85°C, unless otherwise noted. Typical ..
MAX12527ETK+
Dual, 65Msps, 12-Bit, IF/Baseband ADC
General DescriptionThe MAX12527 is a dual 3.3V, 12-bit analog-to-digital
converter (ADC) featuring fully differential wideband
track-and-hold (T/H) inputs, driving internal quantizers.
The MAX12527 is optimized for low power, small size,
and high dynamic performance in intermediate frequen-
cy (IF) and baseband sampling applications. This dual
ADC operates from a single 3.3V supply, consuming
only 620mW while delivering a typical 69.8dB signal-to-
noise ratio (SNR) performance at a 175MHz input fre-
quency. The T/H input stages accept single-ended or
differential inputs up to 400MHz. In addition to low oper-
ating power, the MAX12527 features a 166µW power-
down mode to conserve power during idle periods.
A flexible reference structure allows the MAX12527 to
use the internal 2.048V bandgap reference or accept
an externally applied reference and allows the refer-
ence to be shared between the two ADCs. The refer-
ence structure allows the full-scale analog input range
to be adjusted from ±0.35V to ±1.15V. The MAX12527
provides a common-mode reference to simplify design
and reduce external component count in differential
analog input circuits.
The MAX12527 supports either a single-ended or differ-
ential input clock. User-selectable divide-by-two (DIV2)
and divide-by-four (DIV4) modes allow for design flexibil-
ity and help eliminate the negative effects of clock jitter.
Wide variations in the clock duty cycle are compensated
with the ADC’s internal duty-cycle equalizer (DCE).
The MAX12527 features two parallel, 12-bit-wide,
CMOS-compatible outputs. The digital output format is
pin-selectable to be either two’s complement or Gray
code. A separate power-supply input for the digital out-
puts accepts a 1.7V to 3.6V voltage for flexible interfac-
ing with various logic levels. The MAX12527 is available
in a 10mm x 10mm x 0.8mm, 68-pin thin QFN package
with exposed paddle (EP), and is specified for the
extended (-40°C to +85°C) temperature range.
For a 14-bit, pin-compatible version of this ADC, refer to
the MAX12557 data sheet.
ApplicationsIF and Baseband Communication Receivers
Cellular, LMDS, Point-to-Point Microwave,
MMDS, HFC, WLAN
I/Q Receivers
Ultrasound and Medical Imaging
Portable Instrumentation
Digital Set-Top Boxes
Low-Power Data Acquisition
FeaturesDirect IF Sampling Up to 400MHzExcellent Dynamic Performance
70.4dB/69.8dB SNR at fIN= 70MHz/175MHz
84.4dBc/80.2dBc SFDR at fIN= 70MHz/175MHz3.3V Low Power Operation
647mW (Differential Clock Mode)
620mW (Single-Ended Clock Mode)Fully Differential or Single-Ended Analog InputAdjustable Differential Analog Input Voltage750MHz Input BandwidthAdjustable, Internal or External, Shared Reference Differential or Single-Ended ClockAccepts 25% to 75% Clock Duty CycleUser-Selectable DIV2 and DIV4 Clock ModesPower-Down ModeCMOS Outputs in Two’s Complement or Gray
CodeOut-of-Range and Data-Valid IndicatorsSmall, 68-Pin Thin QFN Package14-Bit Compatible Version Available (MAX12557)Evaluation Kit Available (Order MAX12527 EV Kit)
MAX12527
Dual, 65Msps, 12-Bit, IF/Baseband ADC
Ordering Information
Pin Configuration appears at end of data sheet.*EP = Exposed paddle.
Selector Guide
MAX12527
Dual, 65Msps, 12-Bit, IF/Baseband ADC
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈10pF at digital outputs, VIN= -0.5dBFS (differen-
tial), DIFFCLK/SECLK= OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T= GND, fCLK= 65MHz, TA= -40°C to
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND................................................................-0.3V to +3.6V
OVDDto GND............-0.3V to the lower of (VDD+ 0.3V) and +3.6V
INAP, INAN to GND...-0.3V to the lower of (VDD+ 0.3V) and +3.6V
INBP, INBN to GND...-0.3V to the lower of (VDD+ 0.3V) and +3.6V
CLKP, CLKN to
GND........................-0.3V to the lower of (VDD+ 0.3V) and +3.6V
REFIN, REFOUT
to GND..................-0.3V to the lower of (VDD+ 0.3V) and +3.6V
REFAP, REFAN,
COMA to GND......-0.3V to the lower of (VDD+ 0.3V) and +3.6V
REFBP, REFBN,
COMB to GND......-0.3V to the lower of (VDD+ 0.3V) and +3.6V
DIFFCLK/SECLK, G/T, PD, SHREF, DIV2,
DIV4 to GND.........-0.3V to the lower of (VDD+ 0.3V) and +3.6V
D0A–D11A, D0B–D11B, DAV,
DORA, DORB to GND..............................-0.3V to (OVDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
68-Pin Thin QFN 10mm x 10mm x 0.8mm
(derate 70mW/°C above +70°C)....................................4000mW
Operating Temperature Range................................-40°C to +85°C
Junction Temperature...........................................................+150°C
Storage Temperature Range.................................-65°C to +150°C
Lead Temperature (soldering 10s).......................................+300°C
MAX12527
Dual, 65Msps, 12-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈10pF at digital outputs, VIN= -0.5dBFS (differen-
tial), DIFFCLK/SECLK= OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T= GND, fCLK= 65MHz, TA= -40°C to
MAX12527
Dual, 65Msps, 12-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈10pF at digital outputs, VIN= -0.5dBFS (differen-
tial), DIFFCLK/SECLK= OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T= GND, fCLK= 65MHz, TA= -40°C to
MAX12527
Dual, 65Msps, 12-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈10pF at digital outputs, VIN= -0.5dBFS (differen-
tial), DIFFCLK/SECLK= OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T= GND, fCLK= 65MHz, TA= -40°C to
MAX12527
Dual, 65Msps, 12-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈10pF at digital outputs, VIN= -0.5dBFS (differen-
tial), DIFFCLK/SECLK= OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T= GND, fCLK= 65MHz, TA= -40°C to
MAX12527
Dual, 65Msps, 12-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈10pF at digital outputs, VIN= -0.5dBFS (differen-
tial), DIFFCLK/SECLK= OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T= GND, fCLK= 65MHz, TA= -40°C to
+85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Note 1:Specifications ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.
Note 2:Specifications guaranteed by production test for ≥+25°C.
Note 3:Two-tone intermodulation distortion measured with respect to a single-carrier amplitude, and not the peak-to-average input
power of both input tones.
Note 4:During power-down, D0A–D11A, D0B–D11B, DORA, DORB, and DAV are high impedance.
Note 5:Guaranteed by design and characterization.
Typical Operating Characteristics(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL≈5pF at digital outputs, VIN= -0.5dBFS,
DIFFCLK/SECLK= OVDD, PD = GND, G/T= GND, fCLK= 65MHz (50% duty cycle), TA= +25°C, unless otherwise noted.)
MAX12527
Dual, 65Msps, 12-Bit, IF/Baseband ADC
Typical Operating Characteristics (continued)(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL≈5pF at digital outputs, VIN= -0.5dBFS,
DIFFCLK/SECLK= OVDD, PD = GND, G/T= GND, fCLK= 65MHz (50% duty cycle), TA= +25°C, unless otherwise noted.)
MAX12527
Dual, 65Msps, 12-Bit, IF/Baseband ADC
Typical Operating Characteristics (continued)(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL≈5pF at digital outputs, VIN= -0.5dBFS,
DIFFCLK/SECLK= OVDD, PD = GND, G/T= GND, fCLK= 65MHz (50% duty cycle), TA= +25°C, unless otherwise noted.)
MAX12527
Dual, 65Msps, 12-Bit, IF/Baseband ADC
Typical Operating Characteristics (continued)(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL≈5pF at digital outputs, VIN= -0.5dBFS,
DIFFCLK/SECLK= OVDD, PD = GND, G/T= GND, fCLK= 65MHz (50% duty cycle), TA= +25°C, unless otherwise noted.)
MAX12527
Dual, 65Msps, 12-Bit, IF/Baseband ADC
Typical Operating Characteristics (continued)(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL≈5pF at digital outputs, VIN= -0.5dBFS,
DIFFCLK/SECLK= OVDD, PD = GND, G/T= GND, fCLK= 65MHz (50% duty cycle), TA= +25°C, unless otherwise noted.)
MAX12527
Dual, 65Msps, 12-Bit, IF/Baseband ADC
MAX12527
Dual, 65Msps, 12-Bit, IF/Baseband ADC
MAX12527
Detailed DescriptionThe MAX12527 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half clock cycle.
From input to output the total latency is 8 clock cycles.
Each pipeline converter stage converts its input voltage
to a digital output code. At every stage, except the last,
the error between the input voltage and the digital out-
put code is multiplied and passed along to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. Figure 2 shows the
MAX12527 functional diagram.
Dual, 65Msps, 12-Bit, IF/Baseband ADCFigure 1. Pipeline Architecture—Stage Blocks
