MAX1204AEAP+ ,5V, 8-Channel, Serial, 10-Bit ADC with 3V Digital InterfaceApplications5V/3V Mixed-Supply SystemsTOP VIEW +Data AcquisitionCH0 1 20 VDDProcess ControlCH1 2 19 ..
MAX1204BCAP ,5v, 8-cHANNEL, sERIAL, 10-bIT adc WITH 3v dIGITAL iNTERFACEApplicationsTOP VIEW5V/3V Mixed-Supply Systems20CH0 1 VDDData AcquisitionCH1 2 19 SCLKProcess Cont ..
MAX1205EMH+ ,+5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADCFeaturesThe MAX1205 is a 14-bit, monolithic, analog-to-digital♦ Monolithic, 14-Bit, 1Msps ADCconver ..
MAX1209ETL+ ,12-Bit, 80Msps, 3.3V IF-Sampling ADCfeatures a 3µW power-down to ±1.15Vmode to conserve power during idle periods.♦ Common-Mode Referen ..
MAX120CAG ,500ksps, 12-Bit ADCs with Track/Hold And RefrenceELECTRICAL CHARACTERISTICS
(VDD = +4 75V to +5 25V, Vss = -10EV to -15.75V, (CLN = 8MHZ for MAX120 ..
MAX120CAG ,500ksps, 12-Bit ADCs with Track/Hold And RefrenceApplications
Digital-Signal Processing
Audio and Telecom Processing
Speech Recognition and S ..
MAX3510EEP ,Upstream CATV Amplifier
MAX3510EEP ,Upstream CATV Amplifier
MAX3510EEP ,Upstream CATV Amplifier
MAX3510EEP+ ,Upstream CATV Amplifier
MAX3510EEP+T ,Upstream CATV Amplifier
MAX3510EEP-T ,Upstream CATV Amplifier
MAX1204AEAP+
5V, 8-Channel, Serial, 10-Bit ADC with 3V Digital Interface
_______________General DescriptionThe MAX1204 is a 10-bit data-acquisition system
specifically designed for use in applications with mixed
+5V (analog) and +3V (digital) supply voltages. It oper-
ates with a single +5V analog supply or dual ±5V ana-
log supplies, and combines an 8-channel multiplexer,
internal track/hold, and serial interface with high con-
version speed and low power consumption.
A 4-wire serial interface connects directly to
SPI/MICROWIRE®devices without external logic, and a
serial strobe output allows direct connection to
TMS320-family digital signal processors. The MAX1204
uses either the internal clock or an external serial-inter-
face clock to perform successive-approximation ana-
log-to-digital conversions. The serial interface operates
at up to 2MHz.
The MAX1204 features an internal 4.096V reference and
a reference-buffer amplifier that simplifies gain trim. It
also has a VLpin that supplies power to the digital out-
puts. Output logic levels (3V, 3.3V, or 5V) are determined
by the value of the voltage applied to this pin.
A hard-wired SHDNpin and two software-selectable
power-down modes are provided. Accessing the serial
interface automatically powers up the device. A quick
turn-on time allows the MAX1204 to be shut down
between conversions, enabling the user to optimize
supply currents. By customizing power-down between
conversions, supply current can drop below 10µA at
reduced sampling rates.
The MAX1204 is available in 20-pin SSOP and PDIP
packages, and is specified for the commercial and
extended temperature ranges.
________________________Applications5V/3V Mixed-Supply Systems
Data Acquisition
Process Control
Battery-Powered Instruments
Medical Instruments
____________________________Features8-Channel Single-Ended or 4-Channel Differential
InputsOperates from +5V Single or ±5V Dual SuppliesUser-Adjustable Output Logic Levels (2.7V to
5.25V)Low Power:1.5mA (Operating Mode)
2µA (Power-Down Mode)Internal Track/Hold, 133kHz Sampling RateInternal 4.096V ReferenceSPI/MICROWIRE/TMS320-Compatible 4-Wire
Serial InterfaceSoftware-Configurable Unipolar/Bipolar Inputs20-Pin PDIP/SSOPPin-Compatible 12-Bit Upgrade: MAX1202+TOP VIEW
PDIP/SSOPVDD
SCLK
DIN
SSTRB
DOUT
GND
REFADJ
REFSHDN
VSS
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
MAX1204
__________________Pin Configuration
MAX1204, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
______________Ordering Information
Typical Operating Circuit appears on last page.
Ordering Information continued at end of data sheet.PART TEMP RANGE PIN-
PACKAGE TOP M ARKMAX1204ACPP+0°C to +70°C20 PDIP±1/2
MAX1204BCPP+0°C to +70°C20 PDIP±1
MAX1204ACAP+0°C to +70°C20 SSOP±1/2
MAX1204BCAP+0°C to +70°C20 SSOP±1
+Denotes a lead(Pb)-free/RoHS-compliant package.
MAX1204, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
VL................................................................-0.3V to (VDD+ 0.3V)
VSSto GND...............................................................+0.3V to -6V
VDDto VSS..............................................................-0.3V to +12V
CH0–CH7 to GND............................(VSS- 0.3V) to (VDD+ 0.3V)
CH0–CH7 Total Input Current...........................................±20mA
REF to GND................................................-0.3V to (VDD+ 0.3V)
REFADJ to GND.........................................-0.3V to (VDD+ 0.3V)
Digital Inputs to GND.................................-0.3V to (VDD+ 0.3V)
Digital Outputs to GND.................................-0.3V to (VL+ 0.3V)
Digital Output Sink Current.................................................25mA
Continuous Power Dissipation (TA= +70°C)
PDIP (derate 11.11mW/°C above +70°C).....................889mW
SSOP (derate 8.00mW/°C above +70°C).....................640mW
Operating Temperature Ranges
MAX1204_C_P.....................................................0°C to +70°C
MAX1204_E_P..................................................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Soldering Temperature (reflow).......................................+260°C
ELECTRICAL CHARACTERISTICS(VDD= +5V ±5%, VL= 2.7V to 3.6V; VSS= 0V or -5V ±5%; fSCLK= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); 4.7µF capacitor at REF; TA= TMIN toTMAX; unless otherwise noted.)
MAX1204A
VIN= 4.096VP-P, 65kHz (Note 4)
External reference, 4.096V
MAX1204B
No missing codes over temperature
MAX1204A
MAX1204B
CONDITIONS-75Channel-to-Channel Crosstalk70SFDRSpurious-Free Dynamic Range-70THDTotal Harmonic Distortion
(up to the 5th harmonic)66SINADSignal-to-Noise + Distortion Ratio
LSB±0.5INLRelative Accuracy (Note 2)
Bits10Resolution
LSB±0.1Channel-to-Channel
Offset Matching
ppm/°C±0.8Gain Temperature Coefficient
±1.0
LSB±1.0DNLDifferential Nonlinearity
LSB±1.0Offset Error±2.0
UNITSMINTYPMAXSYMBOLPARAMETER-3dB rolloffMHz4.5Small-Signal Bandwidth
kHz800Full-Power Bandwidth
LSB±1.0Gain Error (Note 3)±2.0
MAX1204A
MAX1204B
DC ACCURACY(Note 1)
DYNAMIC SPECIFICATIONS(10kHz sine-wave input, 4.096VP-P, 133ksps, 2.0MHz external clock, bipolar input mode)
MAX1204, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
ELECTRICAL CHARACTERISTICS (continued)(VDD= +5V ±5%, VL= 2.7V to 3.6V; VSS= 0V or -5V ±5%; fSCLK= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); 4.7µF capacitor at REF; TA= TMIN toTMAX; unless otherwise noted.)
MAX1204AC= +25°C
External clock, 2MHz, 12 clocks/conversion
(Note 6)
On/off leakage current, VCH_= ±5V
Bipolar, VSS= -5V
Unipolar, VSS= 0V
Used for data transfer only
Internal compensation mode (Note 6)
Internal clock
External compensation mode, 4.7µF
CONDITIONSppm/°C
±30±50
VREFTemperature Coefficient30REF Short-Circuit Current4.0764.0964.116REF Output Voltage 16Input Capacitance±0.01±1Multiplexer Leakage Current
±VREF/2VVREFInput Voltage Range, Single-
Ended and Differential (Note 7)2.0
0.10.4MHz
External Clock-Frequency Range
MHz1.7Internal Clock Frequency10Aperture Delay1.5tACQTrack/Hold Acquisition Time5.510tCONVConversion Time (Note 5)
UNITSMINTYPMAXSYMBOLPARAMETERMAX1204AE±30±60
±30MAX1204B
0mA to 0.5mA output loadmV2.5Load Regulation (Note 8)
Internal compensation modeµF0Capacitive Bypass at REFExternal compensation mode4.70.01Capacitive Bypass at REFADJ±1.5REFADJ Adjustment Range2.50VDD+
50mVInput Voltage Range200350Input Current1220Input Resistance
VSHDN= 0VµA1.510REF Input Current in ShutdownVDD-
50mVREFADJ Buffer Disable Threshold <50Aperture Jitter
CONVERSION RATE
INTERNAL REFERENCE
ANALOG INPUT
EXTERNAL REFERENCE AT REF (Buffer disabled, VREF= 4.096V)
MAX1204, 8-Channel, Serial, 10-Bit ADC
with 3V Digital InterfaceInternal compensation mode
Fast power-down (Note 9)
External compensation mode
CONDITIONS0Capacitive Bypass at REF3070IDDPositive Supply Current0 or -5 ±5%VSSNegative Supply Voltage5 ±5%VDDPositive Supply Voltage
V/V1.68Reference-Buffer Gain±50REFADJ Input Current
UNITSMINTYPMAXSYMBOLPARAMETER
ELECTRICAL CHARACTERISTICS (continued)VDD= +5V ±5%, VL= 2.7V to 3.6V; VSS= 0V or -5V ±5%; fSCLK= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); 4.7µF capacitor at REF; TA= TMIN toTMAX; unless otherwise noted.)
Operating modemA1.52.5
Operating mode and fast power-downµA50ISSNegative Supply Current
Full power-down (Note 9)210
Full power-down102.705.25VLLogic Supply Voltage= VDD= 5VµA10IVLLogic Supply Current (Notes 6, 10)
VDD= 5V ±5%; external reference, 4.096V;
full-scale inputmV±0.06±0.5PSRPositive Supply Rejection
(Note 11)
VSS= -5V ±5%; external reference, 4.096V;
full-scale inputmV±0.01±0.5PSRNegative Supply Rejection
(Note 11)
External reference, 4.096V; full-scale inputmV±0.06±0.5PSRLogic Supply Rejection
(Note 12)
EXTERNAL REFERENCE AT REFADJ
POWER REQUIREMENTS
MAX1204, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface= VL(Note 6)= VL
ISOURCE= 1mA
ISINK= 3mA
SHDN= open
VSHDN= 0V
SHDN= VDD
(Note 6)
VIN= 0V or VDD
CONDITIONS15COUTThree-State Output Capacitance±10ILThree-State Leakage CurrentVL- 0.5VOHOutput Voltage High0.4VOLOutput Voltage Low -100100SHDNMaximum Allowed
Leakage, Mid-Input-4.0ISLSHDNInput Current, Low4.0ISHSHDNInput Current, HighVDD - 0.5VSHSHDNInput High Voltage0.8VIL2.0VIHDIN, SCLK, CSInput High Voltage
DIN, SCLK, CSInput Low Voltage15CINDIN, SCLK, CSInput Capacitance±1IINDIN, SCLK, CSInput Leakage0.15VHYSTDIN, SCLK, CSInput Hysteresis
UNITSMINTYPMAXSYMBOLPARAMETER
ELECTRICAL CHARACTERISTICS (VDD= +5V ±5%, VL= 2.7V to 5.25V; VSS= 0V or -5V ±5%; fSCLK= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); 4.7µF capacitor at REF; TA= TMIN toTMAX; unless otherwise noted.)
ISINK= 5mAV0.4VOLOutput Voltage Low ISINK= 8mA0.3
ISINK= 6mA0.3
ISOURCE= 1mAV4VOHOutput Voltage High
VCS= 5VµA±10ILThree-State Leakage Current
VCS= 5V (Note 6)pF15COUTThree-State Output Capacitance1.5VDD- 1.5VSMSHDNInput Mid-Voltage0.5VSLSHDNInput Low Voltage
SHDN= openV2.75VFLTSHDNVoltage, Open
DIGITAL INPUTS: DIN, SCLK, CS, SHDN
DIGITAL OUTPUTS: DOUT, SSTRB(VL= 2.7V to 3.6V)
DIGITAL OUTPUTS: DOUT, SSTRB(VL= 4.75V to 5.25V)
CLOAD= 100pF
MAX1204, 8-Channel, Serial, 10-Bit ADC
with 3V Digital InterfaceExternal clock mode only, CLOAD= 100pFns240
CLOAD= 100pFns20240tDOSCLK Fall to Output Data Valid
CONDITIONS240tDVCSFall to Output Enable
CLOAD= 100pFns240tTRCSRise to Output Disable
tSDVCSFall to SSTRB Output Enable
(Note 6)
External clock mode only, CLOAD= 100pFns240tSTRCSRise to SSTRB Output
Disable (Note 6)
Internal clock mode onlyns0tSCKSSTRB Rise to SCLK Rise
(Note 6)0tDHDIN to SCLK Hold1.5tACQAcquisition Time100tDSDIN to SCLK Setup
UNITSMINTYPMAXSYMBOLPARAMETER
TIMING CHARACTERISTICS(VDD= +5V ±5%, VL= 2.7V to 3.6V, VSS= 0V or -5V ±5%, TA= TMINto TMAX,unless otherwise noted.)100tCSSCSto SCLK Rise Setup0tCSHCSto SCLK Rise Hold200tCHSCLK Pulse Width High200tCLSCLK Pulse Width Low
CLOAD= 100pFns240tSSTRBSCLK Fall to SSTRB
CLOAD= 100pF
Note 1:Tested at VDD= 5.0V; VSS= 0V; unipolar input mode.
Note 2:Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is
calibrated.
Note 3:Internal reference, offset nulled.
Note 4:On-channel grounded; sine-wave applied to all off-channels.
Note 5:Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:Guaranteed by design. Not subject to production testing.
Note 7:Common-mode range for analog inputs is from VSSto VDD.
Note 8:External load should not change during the conversion for specified accuracy.
Note 9:Shutdown supply current is measured with VLat 3.3V, and with all digital inputs tied to either VLor GND (Figure 12c);
REFADJ = GND.
Note 10:Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled (CShigh). When the outputs are
active (CSlow), the logic supply current depends on fSCLK, and on the static and capacitive load at DOUT and SSTRB.
Note 11:Measured at VSUPPLY+5% and VSUPPLY -5% only.
Note 12:Measured at VL= 2.7V and VL= 3.6V.
MAX1204, 8-Channel, Serial, 10-Bit ADC
with 3V Digital InterfaceSUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1204 TOC01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
SUPPLY CURRENT
vs. TEMPERATURE
MAX1204 TOC02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX1204 TOC03
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT (
REFADJ = GND
__________________________________________Typical Operating Characteristics(VDD= 5V ±5%; VL= 2.7V to 3.6V; fSCLK= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
4.7µF capacitor at REF; TA = +25°C; unless otherwise noted.)
NAMEFUNCTION1–8CH0–CH7Sampling Analog InputsVSSNegative Supply Voltage. Tie VSSto -5V ±5% or GND.
PINSHDN
Three-Level Shutdown Input. Pulling SHDNlow shuts the MAX1204 down to 10µA (max) supply
current; otherwise, the MAX1204 is fully operational. Pulling SHDNto VDDputs the reference-buffer
amplifier in internal compensation mode. Letting SHDNfloat puts the reference-buffer amplifier in
external compensation mode.REF
Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer
provides a 4.096V nominal output, externally adjustable at REFADJ. In external reference mode,
disable the internal buffer by pulling REFADJ to VDD.DOUTSerial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CSis high.VLSupply Voltage for Digital Output Pins. Voltage applied to VLdetermines the positive output swing of
the Digital Outputs (DOUT, SSTRB).GNDGround; IN- Input for Single-Ended ConversionsREFADJInput to the Reference-Buffer Amplifier. Tie REFADJ to VDD to disable the reference-buffer amplifier.SCLKSerial-Clock Input. SCLK clocks data in and out of serial interface. In external clock mode, SCLK also
sets the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)CSActive-Low Chip Select. Data is not clocked into DIN unless CSis low. When CSis high, DOUT is
high impedance.DINSerial-Data Input. Data is clocked in at SCLK’s rising edge.SSTRB
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1204 begins the analog-
to-digital conversion and goes high when the conversion is finished. In external clock mode, SSTRB
pulses high for one clock period before the MSB decision. High impedance when CSis high (external
clock mode).
______________________________________________________________Pin Description
MAX1204, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
_______________Detailed DescriptionThe MAX1204 uses a successive-approximation con-
version technique and input track/hold (T/H) circuitry to
convert an analog signal to a 10-bit digital output. A
flexible serial interface provides easy interface to 3V
microprocessors (µPs).Figure 3 is the MAX1204 block
diagram.
Pseudo-Differential InputFigure 4 shows the analog-to-digital converter’s
(ADC’s) analog comparator’s sampling architecture. In
single-ended mode, IN+ is internally switched to
CH0–CH7 and IN-is switched to GND. In differential
mode, IN+ and IN-are selected from pairs of CH0/CH1,
CH2/CH3, CH4/CH5, and CH6/CH7. Configure the
channels using Tables 3 and 4.
In differential mode, IN-and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential such that only the signal at IN+ is
sampled. The return side (IN-) must remain stable with-
in ±0.5 LSB (±0.1 LSB for best results) with respect to
GND during a conversion. To do this, connect a 0.1µF
capacitor from IN-(of the selected analog input) to
GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit is entered. The T/H switch opens at the end of
the acquisition interval, retaining charge on CHOLDas a
sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLDfrom the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN-is sim-
ply GND. This unbalances node ZERO at the compara-
tor’s input. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 10-bit resolution. This
action is equivalent to transferring a charge of 16pF x
[(VIN+) -(VIN-)] from CHOLDto the binary-weighted
capacitive DAC, which in turn forms a digital represen-
tation of the analog input signal.
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable TimeFigure 3. Block Diagram
+3.3V
3kΩ
CLOAD
GND
DOUT
CLOAD
GND
3kΩ
DOUT
a. High-Z to VOH and VOL to VOHb. High-Z to VOL and VOH to VOL
+3.3V
3kΩ
CLOAD
GND
DOUT
CLOAD
GND
3kΩ
DOUT
a. VOH to High-Zb. VOL to High-Z
INPUTSHIFT
REGISTERCONTROL
LOGIC
INT
CLOCK
OUTPUTSHIFT
REGISTER
+2.44VREFERENCE
T/HANALOG
INPUT
MUX
SAR
ADC
DOUT
SSTRB
VDD
VSS
SCLK
DIN
CH0
CH1
CH3
CH2
CH7
CH6
CH5
CH4
GND
REFADJ
REF
OUT
REF
CLOCK
+4.096V
20k≈ 1.68
MAX1204
SHDN
MAX1204, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
Track/HoldThe T/H enters tracking mode on the falling clock edge
after the fifth bit of the 8-bit control word is shifted in. The
T/H enters hold mode on the falling clock edge after the
eighth bit of the control word is shifted in. IN-is connect-
ed to GND if the converter is set up for single-ended
inputs, and the converter samples the “+” input. IN-con-
nects to the “-” input if the converter is set up for differen-
tial inputs, and the difference of ⏐|N+ -IN-⏐ is sampled.
The positive input connects back to IN+ at the end of
the conversion, and CHOLDcharges to the input signal.
The time required for the T/H to acquire an input signal is
a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
acquisition time increases and more time must be
allowed between conversions. The acquisition time,
tACQ,is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by the following:
tACQ= 7 x (RS+ RIN) x 16pF
where RIN= 9kΩ, RS= the source impedance of the
input signal, and tACQis never less than 1.5µs. Note that
source impedances below 4kΩdo not significantly
affect the ADC’s AC performance. Higher source
impedances can be used if an input capacitor is con-
nected to the analog inputs, as shown in Figure 5. Note
that the input capacitor forms an RC filter with the input
source impedance, limiting the ADC’s signal bandwidth.
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
GND
CSWITCH
TRACK
T/H
SWITCH
RIN
CHOLD
HOLD
CAPACITIVE DAC
REF
ZERO
COMPARATOR+
16pF
SINGLE-ENDED MODE:
DIFFERENTIAL MODE:
IN+ = CHO–CH7, IN- = GND.
IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN– CHANNEL.
INPUT
MUX
0.1μF
VDD
GND
VSS
SCLK
DIN
DOUT
SSTRB
SHDN
+3V
N.C.
0.01μF
CH7
REFADJ
REFC2
0.01μF
4.7μF
0V TO
4.096V
ANALOG
INPUT
0.1μF
+3V
OSCILLOSCOPE
CH1CH2CH3CH4
FULL-SCALE ANALOG INPUT
MAX1204
+5V
2MHz
OSCILLATOR
SCLK
SSTRB
DOUT
Figure 4. Equivalent Input Circuit
MAX1204, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
Input BandwidthThe ADC’s input tracking circuitry has a 4.5MHz
small-signal bandwidth. Therefore, it is possible to digi-
tize high-speed transient events and measure periodic
signals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input Range and Input ProtectionInternal protection diodes, which clamp the analog
inputs to VDDand VSS, allow the analog input pins to
swing from (VSS-0.3V) to (VDD+ 0.3V) without dam-
age. However, for accurate conversions near full scale,
the inputs must not exceed VDDby more than 50mV, or
be lower than VSSby 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off-channels over 2mA, as excessive current
degrades on-channel conversion accuracy.The full-scale input voltage depends on the voltage at
REF (Tables 1a and 1b).
Quick LookUse the circuit of Figure 5 to quickly evaluate the
MAX1204’s analog performance. The MAX1204 requires
that a control byte be written to DIN before each conver-
sion. Tying DIN to +3V feeds in control byte $FF hex,
which triggers single-ended unipolar conversions on
CH7 in external clock mode without powering down
between conversions. In external clock mode, the
SSTRB output pulses high for one clock period before
the most significant bit of the conversion result shifts out
of DOUT. Varying the analog input to CH7 alters the
sequence of bits from DOUT. A total of 15 clock cycles
per conversion is required. All SSTRB and DOUT output
transitions occur on SCLK’s falling edge.
How to Start a ConversionClocking a control byte into DIN starts conversion on
the MAX1204. With CSlow, each rising edge on SCLK
clocks a bit from DIN into the MAX1204’s internal shift
register. After CSfalls, the first logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with
no effect. Table 2 shows the control-byte format.
The MAX1204 is fully compatible with MICROWIRE and
SPI devices. For SPI, select the correct clock polarity
and sampling edge in the SPI control registers: set
CPOL = 0 and CPHA = 0. MICROWIRE and SPI both
transmit a byte and receive a byte at the same time.
Using the Typical Operating Circuit, the simplest soft-
ware interface requires only three 8-bit transfers to per-
form a conversion (one 8-bit transfer to configure the
ADC, and two more 8-bit transfers to clock out the con-
version result).
Table 1b.Bipolar Full Scale, Zero Scale,
and Negative Full Scale
Table 1a.Unipolar Full Scale
and Zero Scale
REFERENCEExternal
ZERO
SCALEInternal
at REFADJ
at REF
FULL SCALE+4.096V
VREFADJx 1.68
VREF
REFERENCE-1/2 VREF
-1/2 VREFADJx
-4.096V/2
NEGATIVE
FULL SCALE
ZERO
SCALEInternal
REFADJ
at REF
FULL SCALE+4.096V / 2
+1/2 VREFADJ
x 1.68
+1/2 VREF
External
MAX1204, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
MAX1204
Table 2. Control-Byte Format
Table 3. Channel Selection in Single-Ended Mode (SGL/DIF= 1)
SEL1SEL000
CH4CH5SEL2CH6CH7GND00–+01–+0
CH0–+1
CH1+–1
CH3+–1
CH2+–11+–
Table 4. Channel Selection in Differential Mode (SGL/DIF= 0)
SEL1SEL000
CH4CH5SEL2CH6CH701–+10+–1
CH0+–0
CH1–+0
CH3+–1
CH2–+
PD0
Bit 0
(LSB)SGL/DIF
Bit 2PD1
Bit 1UNI/BIP
Bit 3SEL 0
Bit 4Bit 7
(MSB)SEL 1SEL 2START
Bit 5Bit 6= unipolar, 0= bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0V to VREFcan be converted; in bipolar mode, the signal can range
from -VREF / 2 to +VREF / 2.
= single ended, 0= differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to GND. In differential mode, the voltage dif-
ference between two channels is measured. (Tables 3 and 4.)
Selects clock and power-down modes.
PD1PD0Mode
0Full power-down (IDD= 2µA, internal reference)
1Fast power-down (IDD= 30µA, internal reference)
0Internal clock mode
1External clock mode
These three bits select which of the eight channels is used for the conversion
(Tables 3 and 4).
The first logic 1bit after CSgoes low defines the beginning of the control byte.
DescriptionNameBitUNI/BIP3
SGL/DIF2
PD1
PD0
0 (LSB)
SEL2
SEL1
SEL0
START7 (MSB)
MAX1204, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
Simple Software InterfaceMake sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.Set up the control byte for external clock mode and
call it TB1. TB1’s format should be: 1XXXXX11 binary,
where the Xs denote the particular channel and
conversion mode selected.Use a general-purpose I/O line on the CPU to pullon the MAX1204 low.Transmit TB1 and simultaneously receive a byte
and call it RB1. Ignore RB1.Transmit a byte of all zeros ($00 hex) and simulta-
neously receive byte RB2.Transmit a byte of all zeros ($00 hex) and simulta-
neously receive byte RB3.Pull CSon the MAX1204 high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion padded
with one leading zero, two trailing sub-bits (S1 and S0),
and three trailing zeros. Total conversion time is a func-
tion of the serial clock frequency and the amount of idle
time between 8-bit transfers. To avoid excessive T/H
droop, make sure that the total conversion time does
not exceed 120µs.
Digital OutputIn unipolar input mode, the output is straight binary
(Figure 15); for bipolar inputs, the output is two’s-
complement (Figure 16). Data is clocked out at SCLK’s
falling edge in MSB-first format. The digital output logic
level is adjusted with the VLpin. This allows DOUT and
SSTRB to interface with 3V logic without the risk of
overdrive. The MAX1204’s digital inputs are designed
to be compatible with 3V CMOS logic as well as 5V
logic.
Internal and External Clock ModesThe MAX1204 can use either an external serial clock
or the internal clock to perform the successive-
approximation conversion. In both clock modes, the
external clock shifts data in and out of the MAX1204.
The T/H acquires the input signal as the last three bits
of the control byte are clocked into DIN. Bits PD1 and
PD0 of the control byte program the clock mode.
Figures 7–10 show the timing characteristics common
to both modes.
External ClockIn external clock mode, the external clock not only shifts
data in and out, but it also drives the A/D conversion
steps. SSTRB pulses high for one clock period after the
last bit of the control byte. Successive-approximation bit
decisions are made and appear at DOUT on each of the
next 12 SCLK falling edges (Figure 6). SSTRB and
DOUT go into a high-impedance state when CSgoes
high; after the next CSfalling edge, SSTRB outputs a
logic low. Figure 8 shows the SSTRB timing in external
clock mode.
The conversion must complete in some minimum time or
droop on the sample-and-hold can degrade conversion
results. Use internal clock mode if the clock period
exceeds 10µs or if serial-clock interruptions could cause
the conversion interval to exceed 120µs.
Internal ClockIn internal clock mode, the MAX1204 generates its own
conversion clock. This frees the µP from running the
SAR conversion clock, and allows the conversion
results to be read back at the processor’s convenience,
at any clock rate from zero to 2MHz. SSTRB goes low
at the start of the conversion, then goes high when the
conversion is complete. SSTRB is low for a maximum of
10µs, during which time SCLK should remain low for
best noise performance. An internal register stores data
while the conversion is in progress. SCLK clocks the
data out at this register at any time after the conversion
is complete. After SSTRB goes high, the next falling
clock edge produces the MSB of the conversion at
DOUT, followed by the remaining bits in MSB-first for-
mat (Figure 9). CSdoes not need to be held low once a
conversion is started. Pulling CShigh prevents data
from being clocked into the MAX1204 and three-states
DOUT, but it does not adversely affect an internal
clock-mode conversion already in progress. When
internal clock mode is selected, SSTRB does not go
high impedance when CSgoes high.
Figure 10 shows the SSTRB timing in internal clock
mode. Data can be shifted in and out of the MAX1204 at
clock rates up to 2.0MHz if the acquisition time, tACQ, is
kept above 1.5µs.
