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74F109
Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop
TL/F/9471
54F/74F109
Dual
Positive
Edge-Triggered
Flip-Flop
November 1994
54F/74F109
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The ’F109 consistsoftwo high-speed, completely indepen-
dent transition clockedJK flip-flops.The clocking operation independentofriseandfall timesofthe clock waveform.
TheJK designallows operationasa Dflip-flop (referto ’F74
data sheet)by connectingtheJandK inputs.
Asynchronous Inputs:
LOW inputtoSD setsQto HIGH level
LOW inputtoCD setsQto LOW level
ClearandSetare independentof clock
Simultaneous LOWonCDandSD makes bothQandQ
HIGH
Features Guaranteed 4000V minimum ESD protection.
Commercial Military Package Package DescriptionNumber
74F109PC N16E 16-Lead (0.300× Wide) Molded Dual-in-Line
54F109DM (Note2) J16A 16-Lead CeramicDual-in-Line
74F109SC (Note1) M16A 16-Lead (0.150× Wide) Molded Small Outline, JEDEC
74F109SJ (Note1) M16D 16-Lead (0.300× Wide) Molded Small Outline, EIAJ
54F109FM(Note2) W16A 16-Lead Cerpack
54F109LM (Note2) E20A 16-Lead CeramicLeadless Chip Carrier,TypeC
Note 1:Devicesalso availablein13×reel. UsesuffixeSCXandSJX.
Note 2:Militarygrade devicewith environmentaland burn-in processing.Use suffixe DMQB, FMQBandLMQB.
Logic Symbols Connection Diagrams
TL/F/9471–3
TL/F/9471–4
IEEE/IEC
TL/F/9471–6
Pin Assignment
forDIP, SOICandFlatpak
TL/F/9471–1
Pin Assignment
for LCC
TL/F/9471–2
FASTÉand TRI-STATEÉareregistered trademarks ofNationalSemiconductor Corporation.
C1995National SemiconductorCorporation RRD-B30M75/PrintedinU.S.A.
