74ALVCH16374DGG Fast Delivery |IC PHOENIX CO.,LIMITED

74ALVCH16374DGG ,2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
74ALVCH16374DGG ,2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-stateFeatures and benefits Wide supply voltage range from 1.2 V to 3.6 V Complies with JEDEC standard ..
74ALVCH16374DGGRE4 ,16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 48-TSSOP -40 to 85SCES021L–JULY 1995–REVISED SEPTEMBER 2004ORDERING INFORMATION(1)T PACKAGE ORDERABLE PART NUMBER TOP ..
74ALVCH16374DL ,2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
74ALVCH16374DL ,2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
74ALVCH16374TX ,Low Voltage 16-Bit D-Type Flip-Flop with Busholdapplications with output compatibility up to 3.6V.CC

74ALVCH16374DGG
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
1. General description
The 74ALVCH16374 is 16-bit edge-triggered flip-flop featuring separate D-type inputs for
each flip-flop and 3-state outputs for bus oriented applications.
Incorporates bus hold data inputs which eliminate the need for external pull-up or
pull-down resistors to hold unused inputs.
The 74ALVCH16374 consists of 2 sections of eight edge-triggered flip-flops. A clock (CP)
input and an output enable (OE) are provided per 8-bit section.
The flip-flops will store the state of their individual D-inputs that meet the set-up and hold
time requirements on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the flip-flops are available at the outputs. When OE is
HIGH, the outputs go the high-impedance OFF-state. Operation of the OE input does not
affect the state of the flip-flops.
2. Features and benefits Wide supply voltage range from 1.2 Vto 3.6V Complies with JEDEC standard JESD8-B CMOS low power consumption MULTIBYTE flow-through standard pin-out architecture Low inductance multiple VCC and GND pins for minimum noise and ground bounce Direct interface with TTL levels All data inputs have bus hold Output drive capability 50  transmission lines at 85 C Current drive 24 mA at VCC = 3.0 V
74AL VCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Rev. 5 — 9 July 2012 Product data sheet
NXP Semiconductors 74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information
74ALVCH16374DL 40Cto +85 C SSOP48 plastic shrink small outline package; 48 leads;
body width 7.5 mm
SOT370-1
74LVCH16374DGG 40 Cto+85C TSSOP48 plastic thin shrink small outline package; leads; body width 6.1 mm
SOT362-1
NXP Semiconductors 74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
NXP Semiconductors 74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
5. Pinning information
5.1 Pinning
NXP Semiconductors 74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
5.2 Pin description
6. Functional description
6.1 Function table
[1] H = HIGH voltage level;
L = LOW voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
 = LOW-to-HIGH clock transition;
Z = high-impedance OFF-state.
Table 2. Pin description
1OE, 2OE 1, 24 output enable input (active LOW)
1Q0 to 1Q7 2, 3, 5, 6, 8, 9, 11, 12 3-state flip-flop outputs
2Q0 to 2Q7 13, 14, 16, 17, 19, 20, 22, 23 3-state flip-flop outputs
GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0V)
VCC 7, 18, 31, 42 positive supply voltage
1D0 to 1D7 47, 46, 44, 43, 41, 40, 38, 37 data inputs
2D0 to 2D7 36, 35, 33, 32, 30, 29, 27, 26 data inputs
1CP, 2CP 48, 25 clock input
Table 3. Function table[1]  l L L load and read register  hH H  l L Z load register and disable outputs  hH Z
NXP Semiconductors 74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Above 55 C the value of Ptot derates linearly with 11.3 mW/K.
[3] Above 55 C the value of Ptot derates linearly with 8 mW/K.
8. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +4.6 V
IIK input clamping current VI <0V 50 - mA input voltage control inputs [1] 0.5 +4.6 V
data inputs [1] 0.5 VCC +0.5 V
IOK output clamping current VO >VCC or VO <0V - 50 mA output voltage [1] 0.5 VCC +0.5 V output current VO =0V to VCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb= 40 C to +125 C;
SSOP48 package [2] -850 mW
TSSOP48 package [3] -600 mW
Table 5. Recommended operating conditions
VCC supply voltage maximum speed performance= 30 pF 2.3 - 2.7 V= 50 pF 3.0 - 3.6 V
low voltage applications 1.2 - 3.6 V input voltage data inputs 0 - VCC V
control inputs 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature in free air 40 - +85 C
t/V input transition rise and fall rate VCC = 2.3 V to 3.0 V 0 - 20 ns/V
VCC = 3.0 V to 3.6 V 0 - 10 ns/V
NXP Semiconductors 74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
9. Static characteristics Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Tamb = 40 C to +85 C
VIH HIGH-level input
voltage
VCC = 1.2 V VCC -- V
VCC = 1.8 V 0.7VCC 0.9 - V
VCC = 2.3 V to 2.7 V 1.7 1.2 - V
VCC = 2.7 V to 3.6 V 2.0 1.5 - V
VIL LOW-level input
voltage
VCC = 1.2 V - - 0 V
VCC = 1.8 V - 0.9 0.2VCCV
VCC = 2.3 V to 2.7 V - 1.2 0.7 V
VCC = 2.7 V to 3.6 V - 1.5 0.8 V
VOH HIGH-level output
voltage =VIHorVIL= 100 A; VCC= 1.8Vto 3.6 V VCC 0.2 VCC -V= 6mA; VCC = 1.8 V VCC 0.4 VCC 0.1 - V= 6mA; VCC = 2.3 V VCC 0.3 VCC 0.08 - V= 12 mA; VCC = 2.3 V VCC 0.5 VCC 0.17 - V= 12 mA; VCC = 2.7 V VCC 0.5 VCC 0.14 - V= 18 mA; VCC = 2.3 V VCC 0.6 VCC 0.26 - V= 24 mA; VCC = 3.0 V VCC 1.0 VCC 0.28 - V
VOL LOW-level output
voltage =VIHorVIL= 100 A; VCC= 1.8Vto 3.6 V - 0 0.20 V= 6 mA; VCC = 1.8 V - 0.09 0.30 V =6mA; VCC = 2.3 V - 0.07 0.20 V =12mA; VCC = 2.3 V - 0.15 0.40 V =12mA; VCC = 2.7 V - 0.14 0.40 V= 18 mA; VCC = 2.3 V - 0.23 0.60 V =24mA; VCC = 3.0 V - 0.27 0.55 V input leakage current VCC= 1.8 V to 3.6V
control input; VI= 5.5Vor GND - 0.1 5 A
data input; VI =VCCor GND - 0.1 5 A
IOZ OFF-state output
current =VIHor VIL; VO =VCCor GND
VCC= 1.8 V to 2.7 V - 0.1 5 A
VCC= 2.7 V to 3.6 V - 0.1 10 A
ILIZ OFF-state input
leakage current =VCCor GND
VCC = 1.8 V to 2.7 V - 0.1 10 A
VCC = 3.6 V - 0.1 15 A
ICC supply current VI =VCCor GND; IO =0A;
VCC= 1.8 V to 2.7 V - 0.1 20 A
VCC= 2.7 V to 3.6 V - 0.2 40 A
NXP Semiconductors 74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
[1] All typical values are measured at Tamb =25C.
[2] Valid for data inputs of bus hold parts only.
10. Dynamic characteristics
ICC additional supply
current =VCC 0.6 V; IO =0A; VCC =2.7V
to 3.6 V
per control input - 5 500 A
per data I/O input - 150 750 A
IBHL bus hold LOW current VCC = 2.3 V; VI =0.7V [2] 45 - - A
VCC = 3.0 V; VI =0.8V [2] 75 150 - A
IBHH bus hold HIGH current VCC = 2.3 V; VI =1.7V [2] 45 - - A
VCC = 3.0 V; VI =2.0V [2] 75 175 - A
IBHLO bus hold LOW
overdrive current
VCC = 2.7 V [2] 300 - - A
VCC = 3.6 V [2] 450 - - A
IBHHO bus hold HIGH
overdrive current
VCC = 2.7 V [2] 300 - - A
VCC = 3.6 V [2] 450 - - A input capacitance - 5.0 - pF
Table 6. Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Table 7. Dynamic characteristics
At recommended operating conditions. Voltages are referenced to GND (ground=0 V); test circuit Figure9.
Tamb = 40 C to +85 C
fmax maximum frequency see Figure6
VCC = 1.8 V 125 250 - MHz
VCC = 2.3 V to 2.7 V [2] 150 300 - MHz
VCC = 2.7 V 150 300 - MHz
VCC = 3.0 V to 3.6 V [3] 200 350 - MHz
tpd propagation delay nCPto nQn; see Figure6 [4]
VCC = 1.2 V - 7.7 - ns
VCC = 1.8 V 1.5 3.6 6.5 ns
VCC = 2.3 V to 2.7 V [2] 1.0 2.3 4.3 ns
VCC = 2.7 V 1.0 2.3 3.8 ns
VCC = 3.0 V to 3.6 V [3] 1.0 2.4 3.4 ns
ten enable time nOEto nQn; see Figure7 [4]
VCC = 1.2 V - 8.7 - ns
VCC = 1.8 V 1.5 4.0 7.2 ns
VCC = 2.3 V to 2.7 V [2] 1.0 2.6 4.8 ns
VCC = 2.7 V 1.0 2.9 4.8 ns
VCC = 3.0 V to 3.6 V [3] 1.0 2.3 4.0 ns
NXP Semiconductors 74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
[1] All typical values are measured at Tamb =25C.
[2] Typical values are measured at VCC = 2.5 V.
[3] Typical values are measured at VCC = 3.3 V.
[4] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[5] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi N+ (CL VCC2fo) where: = input frequency in MHz; fo= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in Volts;= number of inputs switching;
(CL VCC2fo)= sum of the outputs.
tdis disable time nOEto nQn; see Figure7 [4]
VCC = 1.2 V - 6.2 - ns
VCC = 1.8 V 1.5 3.1 5.4 ns
VCC = 2.3 V to 2.7 V [2] 1.0 2.1 4.0 ns
VCC = 2.7 V 1.0 2.9 4.5 ns
VCC = 3.0 V to 3.6 V [3] 1.0 2.6 4.1 ns pulse width nCP HIGH or LOW; see Figure6
VCC = 1.8 V 4.0 2.0 - ns
VCC = 2.3 V to 2.7 V [2] 3.0 1.6 - ns
VCC = 2.7 V 3.0 1.6 - ns
VCC = 3.0 V to 3.6 V [3] 2.5 1.4 - ns
tsu set-up time Dn to nCP; see Figure8
VCC = 1.8 V 1.5 0.2 - ns
VCC = 2.3 V to 2.7 V [2] 1.2 0.2 - ns
VCC = 2.7 V 1.5 0.4 - ns
VCC = 3.0 V to 3.6 V [3] 1.2 0.2 - ns hold time Dn to nCP; see Figure8
VCC = 1.8 V 0.6 0.2 - ns
VCC = 2.3 V to 2.7 V [2] 0.8 0.1 - ns
VCC = 2.7 V 0.6 0.2 - ns
VCC = 3.0 V to 3.6 V [3] 0.8 0.0 - ns
CPD power dissipation
capacitance
per flip-flop; VI =GNDto VCC [5]
outputs enabled - 16 - pF
outputs disabled - 10 - pF
Table 7. Dynamic characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground=0 V); test circuit Figure9.

Partno	Mfg	Dc	Qty	Available	Descript
74ALVCH16374DGG	NXP	N/a	39	avai	2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state